From 65f558f576ac716b0639d8d18834b776a2a9f90b Mon Sep 17 00:00:00 2001 From: Fred Reitberger Date: Fri, 1 Apr 2022 16:13:18 -0400 Subject: [PATCH] soc/amd/common/block/spi/fch_spi_ctrl: Fix restricted command write The SPI_RESTRICTED_CMD register is not a PCI configuration register. It is memory mapped from the SPI bar. Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243 rev 1.50 TEST=Compile tested only Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b Signed-off-by: Fred Reitberger Reviewed-on: https://review.coreboot.org/c/coreboot/+/63305 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/spi/fch_spi_ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index 519503dc6d..b3d7c69a68 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -282,7 +282,7 @@ static int fch_spi_flash_protect(const struct spi_flash *flash, const struct reg } /* Final steps to protect region */ - pci_write_config32(SOC_LPC_DEV, SPI_RESTRICTED_CMD1, reg32); + spi_write32(SPI_RESTRICTED_CMD1, reg32); reg32 = spi_read32(SPI_CNTRL0); reg32 &= ~SPI_ACCESS_MAC_ROM_EN; spi_write32(SPI_CNTRL0, reg32);