southbridge/amd: Remove trailing whitespace
Change-Id: I25cdfe6b3c8067793620677c62251e78704f7851 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6334 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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@ -17,8 +17,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#ifndef _HUDSON_EARLY_SETUP_C_
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#ifndef _HUDSON_EARLY_SETUP_C_
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#define _HUDSON_EARLY_SETUP_C_
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#define _HUDSON_EARLY_SETUP_C_
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#include <stdint.h>
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#include <stdint.h>
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#include <arch/io.h>
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#include <arch/io.h>
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@ -17,8 +17,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#ifndef _HUDSON_SMBUS_C_
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#ifndef _HUDSON_SMBUS_C_
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#define _HUDSON_SMBUS_C_
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#define _HUDSON_SMBUS_C_
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#include <io.h>
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#include <io.h>
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#include <stdint.h>
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#include <stdint.h>
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@ -21,8 +21,8 @@
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*
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*
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*/
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*/
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#ifndef _AMD_SBPLATFORM_H_
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#ifndef _AMD_SBPLATFORM_H_
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#define _AMD_SBPLATFORM_H_
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#define _AMD_SBPLATFORM_H_
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#include <stddef.h>
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#include <stddef.h>
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@ -162,7 +162,7 @@ typedef union _PCI_ADDR {
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#include <spi-generic.h>
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#include <spi-generic.h>
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#endif
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#endif
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#define BIOSRAM_INDEX 0xcd4
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#define BIOSRAM_INDEX 0xcd4
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#define BIOSRAM_DATA 0xcd5
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#define BIOSRAM_DATA 0xcd5
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#endif // _AMD_SBPLATFORM_H_
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#endif // _AMD_SBPLATFORM_H_
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@ -21,8 +21,8 @@
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*
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*
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*/
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*/
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#ifndef _AMD_SBPLATFORM_H_
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#ifndef _AMD_SBPLATFORM_H_
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#define _AMD_SBPLATFORM_H_
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#define _AMD_SBPLATFORM_H_
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#include <stddef.h>
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#include <stddef.h>
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@ -107,48 +107,48 @@ typedef union _PCI_ADDR {
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* FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
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* FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
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* FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
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* FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
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*/
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*/
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#define SB_CIMx_PARAMETER 0x02
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#define SB_CIMx_PARAMETER 0x02
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// Generic
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// Generic
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#define cimSpreadSpectrumDefault TRUE
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#define cimSpreadSpectrumDefault TRUE
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#define cimSpreadSpectrumTypeDefault 0x00 // Normal
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#define cimSpreadSpectrumTypeDefault 0x00 // Normal
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#define cimHpetTimerDefault TRUE
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#define cimHpetTimerDefault TRUE
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#define cimHpetMsiDisDefault FALSE // Enable
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#define cimHpetMsiDisDefault FALSE // Enable
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#define cimIrConfigDefault 0x00 // Disable
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#define cimIrConfigDefault 0x00 // Disable
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#define cimSpiFastReadEnableDefault 0x00 // Disable
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#define cimSpiFastReadEnableDefault 0x00 // Disable
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#define cimSpiFastReadSpeedDefault 0x00 // NULL
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#define cimSpiFastReadSpeedDefault 0x00 // NULL
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// GPP/AB Controller
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// GPP/AB Controller
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#define cimNbSbGen2Default TRUE
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#define cimNbSbGen2Default TRUE
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#define cimAlinkPhyPllPowerDownDefault TRUE
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#define cimAlinkPhyPllPowerDownDefault TRUE
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#define cimResetCpuOnSyncFloodDefault TRUE
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#define cimResetCpuOnSyncFloodDefault TRUE
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#define cimGppGen2Default FALSE
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#define cimGppGen2Default FALSE
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#define cimGppMemWrImproveDefault TRUE
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#define cimGppMemWrImproveDefault TRUE
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#define cimGppPortAspmDefault FALSE
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#define cimGppPortAspmDefault FALSE
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#define cimGppLaneReversalDefault FALSE
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#define cimGppLaneReversalDefault FALSE
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#define cimGppPhyPllPowerDownDefault TRUE
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#define cimGppPhyPllPowerDownDefault TRUE
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// USB Controller
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// USB Controller
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#define cimUsbPhyPowerDownDefault FALSE
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#define cimUsbPhyPowerDownDefault FALSE
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// GEC Controller
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// GEC Controller
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#define cimSBGecDebugBusDefault FALSE
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#define cimSBGecDebugBusDefault FALSE
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#define cimSBGecPwrDefault 0x03
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#define cimSBGecPwrDefault 0x03
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// Sata Controller
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// Sata Controller
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#define cimSataSetMaxGen2Default 0x00
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#define cimSataSetMaxGen2Default 0x00
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#define cimSATARefClkSelDefault 0x10
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#define cimSATARefClkSelDefault 0x10
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#define cimSATARefDivSelDefault 0x80
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#define cimSATARefDivSelDefault 0x80
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#define cimSataAggrLinkPmCapDefault TRUE
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#define cimSataAggrLinkPmCapDefault TRUE
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#define cimSataPortMultCapDefault TRUE
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#define cimSataPortMultCapDefault TRUE
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#define cimSataPscCapDefault 0x00 // Enable
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#define cimSataPscCapDefault 0x00 // Enable
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#define cimSataSscCapDefault 0x00 // Enable
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#define cimSataSscCapDefault 0x00 // Enable
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#define cimSataFisBasedSwitchingDefault FALSE
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#define cimSataFisBasedSwitchingDefault FALSE
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#define cimSataCccSupportDefault FALSE
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#define cimSataCccSupportDefault FALSE
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#define cimSataClkAutoOffDefault FALSE
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#define cimSataClkAutoOffDefault FALSE
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#define cimNativepciesupportDefault FALSE
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#define cimNativepciesupportDefault FALSE
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// Fusion Related
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// Fusion Related
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#define cimAcDcMsgDefault FALSE
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#define cimAcDcMsgDefault FALSE
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#define cimTimerTickTrackDefault FALSE
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#define cimTimerTickTrackDefault FALSE
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#define cimClockInterruptTagDefault FALSE
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#define cimClockInterruptTagDefault FALSE
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#define cimOhciTrafficHandingDefault FALSE
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#define cimOhciTrafficHandingDefault FALSE
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#define cimEhciTrafficHandingDefault FALSE
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#define cimEhciTrafficHandingDefault FALSE
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#define cimFusionMsgCMultiCoreDefault FALSE
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#define cimFusionMsgCMultiCoreDefault FALSE
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#define cimFusionMsgCStageDefault FALSE
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#define cimFusionMsgCStageDefault FALSE
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#endif // _AMD_SBPLATFORM_H_
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#endif // _AMD_SBPLATFORM_H_
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@ -17,8 +17,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#ifndef _SB800_EARLY_SETUP_C_
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#ifndef _SB800_EARLY_SETUP_C_
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#define _SB800_EARLY_SETUP_C_
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#define _SB800_EARLY_SETUP_C_
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#include <reset.h>
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#include <reset.h>
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#include <arch/acpi.h>
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#include <arch/acpi.h>
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#ifndef _SB800_SMBUS_C_
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#ifndef _SB800_SMBUS_C_
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#define _SB800_SMBUS_C_
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#define _SB800_SMBUS_C_
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#include "smbus.h"
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#include "smbus.h"
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