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vendorcode/amd/fsp/cezanne: add UPD structs from FSP build 

There will be incompatible changes during the further development of the
coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct
size to match the one in the FSP header. See CB:50241 for details.

Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-02-02 22:17:01 +01:00
parent c0dbd4cb56
commit 65fd33f95f
2 changed files with 99 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
src/vendorcode/amd/fsp/cezanne/FspmUpd.h
View File

@ -12,7 +12,61 @@
/** Fsp M Configuration
**/
typedef struct __packed {
uint16_t UpdTerminator;
/** Offset 0x0040**/ uint32_t pci_express_base_addr;
/** Offset 0x0044**/ uint32_t serial_port_base;
/** Offset 0x0048**/ uint32_t serial_port_use_mmio;
/** Offset 0x004C**/ uint32_t serial_port_stride;
/** Offset 0x0050**/ uint32_t serial_port_baudrate;
/** Offset 0x0054**/ uint32_t serial_port_refclk;
/** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope_mA;
/** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2_mA;
/** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3_mA;
/** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4_mA;
/** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5_mA;
/** Offset 0x006C**/ uint32_t telemetry_vddcr_vdd_offset;
/** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope_mA;
/** Offset 0x0074**/ uint32_t telemetry_vddcr_soc_offset;
/** Offset 0x0078**/ uint8_t aa_mode_en;
/** Offset 0x0079**/ uint8_t unused2;
/** Offset 0x007A**/ uint8_t unused3;
/** Offset 0x007B**/ uint8_t unused4;
/** Offset 0x007C**/ uint32_t fast_ppt_limit_mW;
/** Offset 0x0080**/ uint32_t slow_ppt_limit_mW;
/** Offset 0x0084**/ uint32_t slow_ppt_time_constant_s;
/** Offset 0x0088**/ uint32_t psi0_current_limit_mA;
/** Offset 0x008C**/ uint32_t psi0_soc_current_limit_mA;
/** Offset 0x0090**/ uint32_t thermctl_limit_degreeC;
/** Offset 0x0094**/ uint32_t vrm_maximum_current_limit_mA;
/** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit_mA;
/** Offset 0x009C**/ uint32_t sustained_power_limit_mW;
/** Offset 0x00A0**/ uint32_t stapm_time_constant_s;
/** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time_ms;
/** Offset 0x00A8**/ uint32_t vrm_current_limit_mA;
/** Offset 0x00AC**/ uint32_t vrm_soc_current_limit_mA;
/** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin_mV;
/** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin_mV;
/** Offset 0x00B8**/ uint32_t smu_feature_control_defines;
/** Offset 0x00BC**/ uint32_t smu_feature_control_defines_ext;
/** Offset 0x00C0**/ uint8_t sb_tsi_alert_comparator_mode_en;
/** Offset 0x00C1**/ uint8_t system_config;
/** Offset 0x00C2**/ uint8_t core_dldo_bypass;
/** Offset 0x00C3**/ uint8_t min_soc_vid_offset;
/** Offset 0x00C4**/ uint8_t aclk_dpm0_freq_400MHz;
/** Offset 0x00C5**/ uint8_t unused5;
/** Offset 0x00C6**/ uint8_t unused6;
/** Offset 0x00C7**/ uint8_t sata_enable;
/** Offset 0x00C8**/ uint32_t tseg_size;
/** Offset 0x00CC**/ uint8_t pspp_policy;
/** Offset 0x00CD**/ uint8_t audio_soundwire;
/** Offset 0x00CE**/ uint8_t hd_audio_enable;
/** Offset 0x00CF**/ uint8_t unused9;
/** Offset 0x00D0**/ uint32_t bert_size;
/** Offset 0x00D4**/ uint8_t UnusedUpdSpace0;
/** Offset 0x00D5**/ uint8_t ccx_down_core_mode;
/** Offset 0x00D6**/ uint8_t ccx_disable_smt;
/** Offset 0x00D7**/ uint8_t UnusedUpdSpace1[41];
/** Offset 0x0100**/ uint16_t Reserved100;
/** Offset 0x0102**/ uint16_t UpdTerminator;
} FSP_M_CONFIG;
/** Fsp M UPD Configuration

45
src/vendorcode/amd/fsp/cezanne/FspsUpd.h
View File

@ -10,7 +10,50 @@
#include <FspUpd.h>
typedef struct __packed {
uint16_t UpdTerminator;
/** Offset 0x0020**/ uint32_t emmc0_mode;
/** Offset 0x0024**/ uint16_t emmc0_init_khz_preset;
/** Offset 0x0026**/ uint8_t emmc0_sdr104_hs400_driver_strength;
/** Offset 0x0027**/ uint8_t emmc0_ddr50_driver_strength;
/** Offset 0x0028**/ uint8_t emmc0_sdr50_driver_strength;
/** Offset 0x0029**/ uint8_t unused0[7];
/** Offset 0x0030**/ uint8_t dxio_descriptor0[16];
/** Offset 0x0040**/ uint8_t dxio_descriptor1[16];
/** Offset 0x0050**/ uint8_t dxio_descriptor2[16];
/** Offset 0x0060**/ uint8_t dxio_descriptor3[16];
/** Offset 0x0070**/ uint8_t dxio_descriptor4[16];
/** Offset 0x0080**/ uint8_t dxio_descriptor5[16];
/** Offset 0x0090**/ uint8_t dxio_descriptor6[16];
/** Offset 0x00A0**/ uint8_t dxio_descriptor7[16];
/** Offset 0x00B0**/ uint8_t unused1[16];
/** Offset 0x00C0**/ uint32_t ddi_descriptor0;
/** Offset 0x00C4**/ uint32_t ddi_descriptor1;
/** Offset 0x00C8**/ uint32_t ddi_descriptor2;
/** Offset 0x00CC**/ uint32_t ddi_descriptor3;
/** Offset 0x00D0**/ uint8_t unused2[16];
/** Offset 0x00E0**/ uint8_t fch_usb_version_major;
/** Offset 0x00E1**/ uint8_t fch_usb_version_minor;
/** Offset 0x00E2**/ uint8_t fch_usb_2_port0_phy_tune[9];
/** Offset 0x00EB**/ uint8_t fch_usb_2_port1_phy_tune[9];
/** Offset 0x00F4**/ uint8_t fch_usb_2_port2_phy_tune[9];
/** Offset 0x00FD**/ uint8_t fch_usb_2_port3_phy_tune[9];
/** Offset 0x0106**/ uint8_t fch_usb_2_port4_phy_tune[9];
/** Offset 0x010F**/ uint8_t fch_usb_2_port5_phy_tune[9];
/** Offset 0x0118**/ uint8_t fch_usb_device_removable;
/** Offset 0x0119**/ uint8_t fch_usb_3_port_force_gen1;
/** Offset 0x011A**/ uint8_t fch_usb_u3_rx_det_wa_enable;
/** Offset 0x011B**/ uint8_t fch_usb_u3_rx_det_wa_portmap;
/** Offset 0x011C**/ uint8_t fch_usb_early_debug_select_enable;
/** Offset 0x011D**/ uint8_t unused3;
/** Offset 0x011E**/ uint32_t xhci_oc_pin_select;
/** Offset 0x0122**/ uint8_t xhci0_force_gen1;
/** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable;
/** Offset 0x0124**/ uint32_t gnb_ioapic_base;
/** Offset 0x0128**/ uint8_t gnb_ioapic_id;
/** Offset 0x0129**/ uint8_t fch_ioapic_id;
/** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6];
/** Offset 0x0130**/ uint8_t unused4[16];
/** Offset 0x0140**/ uint8_t UnusedUpdSpace1[16];
/** Offset 0x0150**/ uint16_t UpdTerminator;
} FSP_S_CONFIG;
/** Fsp S UPD Configuration