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soc/intel/quark: Add host bridge access support 

Add host bridge register access routines and macros.

TEST=Build and run on Galileo Gen2

Change-Id: I52eb6a68e99533fbb69c0ae1e6d581e4c4fab9d2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15593
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2016-07-10 17:09:24 -07:00
parent 89186b2eb8
commit 660c67a01f
2 changed files with 51 additions and 0 deletions
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23
src/soc/intel/quark/include/soc/reg_access.h
View File

@ -36,6 +36,7 @@ enum {
PCIE_AFE_REGS,
PCIE_RESET,
GPE0_REGS,
HOST_BRIDGE,
};
enum {
@ -89,6 +90,27 @@ enum {
#define REG_GPIO_XOR(reg_, value_) \
REG_GPIO_RXW(reg_, 0xffffffff, value_)
/* Host bridge register access macros */
#define REG_HOST_BRIDGE_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
HOST_BRIDGE)
#define REG_HOST_BRIDGE_READ(reg_) \
REG_HOST_BRIDGE_ACCESS(READ, reg_, 0, 0, 0)
#define REG_HOST_BRIDGE_WRITE(reg_, value_) \
REG_HOST_BRIDGE_ACCESS(WRITE, reg_, 0, value_, 0)
#define REG_HOST_BRIDGE_AND(reg_, value_) \
REG_HOST_BRIDGE_RMW(reg_, value_, 0)
#define REG_HOST_BRIDGE_RMW(reg_, mask_, value_) \
REG_HOST_BRIDGE_ACCESS(RMW, reg_, mask_, value_, 0)
#define REG_HOST_BRIDGE_RXW(reg_, mask_, value_) \
REG_HOST_BRIDGE_ACCESS(RXW, reg_, mask_, value_, 0)
#define REG_HOST_BRIDGE_OR(reg_, value_) \
REG_HOST_BRIDGE_RMW(reg_, 0xffffffff, value_)
#define REG_HOST_BRIDGE_POLL(reg_, mask_, value_, timeout_) \
REG_HOST_BRIDGE_ACCESS(POLL, reg_, mask_, value_, timeout_)
#define REG_HOST_BRIDGE_XOR(reg_, value_) \
REG_HOST_BRIDGE_RXW(reg_, 0xffffffff, value_)
/* Legacy GPIO register access macros */
#define REG_LEG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
@ -208,6 +230,7 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
uint32_t mdr_read(void);
void mdr_write(uint32_t value);
void mea_write(uint32_t reg_address);
uint32_t reg_host_bridge_unit_read(uint32_t reg_address);
uint32_t reg_legacy_gpio_read(uint32_t reg_address);
void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value);
uint32_t reg_rmu_temp_read(uint32_t reg_address);

28
src/soc/intel/quark/reg_access.c
View File

@ -120,6 +120,24 @@ static void reg_gpio_write(uint32_t reg_address, uint32_t value)
*get_gpio_address(reg_address) = value;
}
uint32_t reg_host_bridge_unit_read(uint32_t reg_address)
{
/* Read the host bridge register */
mea_write(reg_address);
mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
reg_address);
return mdr_read();
}
static void reg_host_bridge_unit_write(uint32_t reg_address, uint32_t value)
{
/* Write the host bridge register */
mea_write(reg_address);
mdr_write(value);
mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
reg_address);
}
uint32_t reg_legacy_gpio_read(uint32_t reg_address)
{
/* Read the legacy GPIO register */
@ -225,6 +243,11 @@ static uint64_t reg_read(struct reg_script_context *ctx)
value = reg_gpio_read(step->reg);
break;
case HOST_BRIDGE:
ctx->display_prefix = "Host Bridge";
value = reg_host_bridge_unit_read(step->reg);
break;
case LEG_GPIO_REGS:
ctx->display_prefix = "Legacy GPIO";
value = reg_legacy_gpio_read(step->reg);
@ -274,6 +297,11 @@ static void reg_write(struct reg_script_context *ctx)
reg_gpio_write(step->reg, (uint32_t)step->value);
break;
case HOST_BRIDGE:
ctx->display_prefix = "Host Bridge";
reg_host_bridge_unit_write(step->reg, (uint32_t)step->value);
break;
case LEG_GPIO_REGS:
ctx->display_prefix = "Legacy GPIO";
reg_legacy_gpio_write(step->reg, (uint32_t)step->value);