diff --git a/src/soc/mediatek/mt8195/include/soc/pll.h b/src/soc/mediatek/mt8195/include/soc/pll.h
index cc133c8b14..9b6f314f65 100644
--- a/src/soc/mediatek/mt8195/include/soc/pll.h
+++ b/src/soc/mediatek/mt8195/include/soc/pll.h
@@ -580,4 +580,45 @@ DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24)
 DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4)
 DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16)
 
+enum {
+	INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = (0x1f << 12) | (0x1 << 17) | (0x1 << 18),
+	INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = (0x10 << 12) | (0x1 << 17) | (0x0 << 18),
+	INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = (0x1 << 0) |
+					      (0x1 << 1) |
+					      (0x1 << 3) |
+					      (0x1 << 4) |
+					      (0x1f << 5) |
+					      (0x1 << 20) |
+					      (0x1 << 23) |
+					      (0x1 << 30),
+	INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = (0x1 << 0) |
+					    (0x1 << 1) |
+					    (0x0 << 3) |
+					    (0x0 << 4) |
+					    (0x10 << 5) |
+					    (0x1 << 20) |
+					    (0x1 << 23) |
+					    (0x1 << 30),
+	INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = (0xf << 0),
+	INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = (0x0 << 0),
+	INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = (0x1 << 0) |
+					     (0x1 << 1) |
+					     (0x1 << 3) |
+					     (0x1 << 4) |
+					     (0x1f << 5) |
+					     (0x1f << 15) |
+					     (0x1 << 20) |
+					     (0x1 << 21),
+	INFRACFG_AO_PERI_BUS_DCM_REG0_ON = (0x1 << 0) |
+					   (0x1 << 1) |
+					   (0x0 << 3) |
+					   (0x0 << 4) |
+					   (0x1f << 5) |
+					   (0x1f << 15) |
+					   (0x1 << 20) |
+					   (0x1 << 21),
+	INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = (0x1 << 29) | (0x1 << 31),
+	INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = (0x1 << 29) | (0x1 << 31),
+};
+
 #endif /* SOC_MEDIATEK_MT8195_PLL_H */
diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c
index fc165358c9..ebdc37f362 100644
--- a/src/soc/mediatek/mt8195/pll.c
+++ b/src/soc/mediatek/mt8195/pll.c
@@ -713,6 +713,27 @@ void mt_pll_init(void)
 	setbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, 0x3 << 21);
 	setbits32(&mt8195_infracfg_ao_bcrm->vdnr_dcm_top_infra_ctrl0, 0x2);
 
+	/* dcm_infracfg_ao_aximem_bus_dcm */
+	clrsetbits32(&mt8195_infracfg_ao->infra_aximem_idle_bit_en_0,
+		     INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK,
+		     INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON);
+	/* dcm_infracfg_ao_infra_bus_dcm */
+	clrsetbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl,
+		     INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK,
+		     INFRACFG_AO_INFRA_BUS_DCM_REG0_ON);
+	/* dcm_infracfg_ao_infra_rx_p2p_dcm */
+	clrsetbits32(&mt8195_infracfg_ao->p2p_rx_clk_on,
+		     INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK,
+		     INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON);
+	/* dcm_infracfg_ao_peri_bus_dcm */
+	clrsetbits32(&mt8195_infracfg_ao->peri_bus_dcm_ctrl,
+		     INFRACFG_AO_PERI_BUS_DCM_REG0_MASK,
+		     INFRACFG_AO_PERI_BUS_DCM_REG0_ON);
+	/* dcm_infracfg_ao_peri_module_dcm */
+	clrsetbits32(&mt8195_infracfg_ao->peri_bus_dcm_ctrl,
+		     INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK,
+		     INFRACFG_AO_PERI_MODULE_DCM_REG0_ON);
+
 	/* initialize SPM request */
 	setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff);