soc/intel/apollolake: Reset GPI IS & IE registers at ramstage

Reset GPI Interrupt status and enable registers from ramstage instead of
bootblock so that it applies to devices in field.

BUG=b:130593883
BRANCH=octopus
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.

Change-Id: Ib11b580ceb23bd1fe789f549b667a8ced2d859a1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32534
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/apollolake/bootblock/bootblock.c

@@ -122,12 +122,3 @@ void bootblock_soc_early_init(void)
 		paging_enable_for_car("pdpt", "pt");
 	}
 }
-
-void bootblock_soc_init(void)
-{
-	/*
-	 * Clear the GPI interrupt enable & status registers to avoid any
-	 * interrupt storm during the kernel bootup.
-	 */
-	gpi_clear_int_cfg();
-}

src/soc/intel/apollolake/chip.c

@@ -395,6 +395,12 @@ static void soc_init(void *data)
 	 * default policy that doesn't honor boards' requirements. */
 	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 
+	/*
+	 * Clear the GPI interrupt status and enable registers. These
+	 * registers do not get reset to default state when booting from S5.
+	 */
+	gpi_clear_int_cfg();
+
 	fsp_silicon_init(romstage_handoff_is_resume());
 
 	/* Restore GPIO IRQ polarities back to previous settings. */