diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 71aa2086d5..fa98cd41a7 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -186,6 +186,8 @@ struct soc_intel_cannonlake_config {
 	uint8_t EmmcHs400RxStrobeDll1;
 	/* 0-78: number of active delay for TX data, unit is 125 psec */
 	uint8_t EmmcHs400TxDataDll;
+	/* Enable/disable SD card write protect pin configuration on CML */
+	uint8_t ScsSdCardWpPinEnabled;
 
 	/* Integrated Sensor */
 	uint8_t PchIshEnable;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 0f27c47bac..494c1db3fb 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -336,6 +336,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->ScsSdCardEnabled = dev->enabled;
 		params->SdCardPowerEnableActiveHigh =
 			CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
+#if CONFIG(SOC_INTEL_COMETLAKE)
+		params->ScsSdCardWpPinEnabled = config->ScsSdCardWpPinEnabled;
+#endif
 	}
 
 	dev = pcidev_path_on_root(PCH_DEVFN_UFS);