lenovo/g505s: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: Ia65f9ecb62767424744e399a43e4728666fd28b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -15,14 +15,13 @@
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#include "AGESA.h"
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <cbfs.h>
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#include <southbridge/amd/agesa/hudson/imc.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
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#include <stdlib.h>
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_DO_RESET, agesa_Reset },
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@ -32,7 +31,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
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{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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@ -171,41 +169,16 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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}
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}
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/**
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* Fch Oem setting callback
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*
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* Configure platform specific Hudson device,
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* such Azalia, SATA, IMC etc.
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*/
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
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void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
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{
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AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
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FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
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FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams_reset->FchReset.Xhci1Enable = FALSE;
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} else if (StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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}
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void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
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{
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/* Azalia Controller OEM Codec Table Pointer */
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FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
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/* Azalia Controller Front Panel OEM Table Pointer */
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/* Fan Control */
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oem_fan_control(FchParams_env);
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/* XHCI configuration */
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FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams_env->Usb.Xhci1Enable = FALSE;
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/* sata configuration */
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}
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printk(BIOS_DEBUG, "Done\n");
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return AGESA_SUCCESS;
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}
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@ -18,7 +18,6 @@ if BOARD_LENOVO_G505S
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SYSTEM_TYPE_LAPTOP
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select AGESA_LEGACY_WRAPPER
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select CPU_AMD_AGESA_FAMILY15_TN
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select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
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select SOUTHBRIDGE_AMD_AGESA_HUDSON
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@ -17,7 +17,7 @@
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#include "AGESA.h"
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#include "amdlib.h"
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
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#include <PlatformMemoryConfiguration.h>
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@ -140,6 +140,13 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
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},
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};
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void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
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{
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FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
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FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchReset->Xhci1Enable = FALSE;
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}
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/*---------------------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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@ -156,7 +163,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
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**/
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/*---------------------------------------------------------------------------------------*/
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static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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AGESA_STATUS Status;
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PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
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@ -188,14 +195,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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PcieComplexListPtr->DdiLinkList = DdiList;
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InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
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return AGESA_SUCCESS;
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}
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static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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return AGESA_SUCCESS;
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}
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/*----------------------------------------------------------------------------------------
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@ -210,7 +209,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
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* If PlatformSpecificTable is populated, AGESA will base its settings on the
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* data from the table. Otherwise, it will use its default conservative settings
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*/
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CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
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NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
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NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
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@ -222,7 +221,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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PSO_END
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};
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const struct OEM_HOOK OemCustomize = {
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.InitEarly = OemInitEarly,
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.InitMid = OemInitMid,
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};
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void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
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{
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InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
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}
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void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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}
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@ -13,7 +13,7 @@
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* GNU General Public License for more details.
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*/
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include "ec.h"
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@ -43,9 +43,7 @@ static void mainboard_enable(device_t dev)
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hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
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hudson_enable_smi_generation();
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if (acpi_is_wakeup_s3())
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agesawrapper_fchs3earlyrestore();
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else
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if (!acpi_is_wakeup_s3())
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pavilion_cold_boot_init();
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}
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