soc/intel/xeon_sp: Refactor code to allow for additional CPUs types

Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.

This is a preparation for future work that will enable next
generation server CPU.

TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/ocp/tiogapass/Kconfig

@@ -19,10 +19,9 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_32768
 	select HAVE_ACPI_TABLES
-	select SOC_INTEL_XEON_SP
 	select MAINBOARD_USES_FSP2_0
-	select FSP_CAR
 	select IPMI_KCS
+	select SOC_INTEL_SKYLAKE_SP
 
 config MAINBOARD_DIR
 	string

src/mainboard/ocp/tiogapass/devicetree.cb

@@ -13,7 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
-chip soc/intel/xeon_sp
+chip soc/intel/xeon_sp/skx
 
 	register "pirqa_routing" = "PCH_IRQ11"
 	register "pirqb_routing" = "PCH_IRQ10"

src/mainboard/ocp/tiogapass/dsdt.asl

@@ -28,12 +28,12 @@ DefinitionBlock(
 	#include "acpi/platform.asl"
 
 	// global NVS and variables
-	#include <soc/intel/xeon_sp/acpi/globalnvs.asl>
+	#include <soc/intel/xeon_sp/skx/acpi/globalnvs.asl>
 
 	#include <cpu/intel/common/acpi/cpu.asl>
 
 	// Xeon-SP ACPI tables
 	Scope (\_SB) {
-		#include <soc/intel/xeon_sp/acpi/uncore.asl>
+		#include <soc/intel/xeon_sp/skx/acpi/uncore.asl>
 	}
 }

src/soc/intel/xeon_sp/Kconfig

@@ -13,14 +13,20 @@
 ## GNU General Public License for more details.
 ##
 
-config SOC_INTEL_XEON_SP
+source "src/soc/intel/xeon_sp/skx/Kconfig"
+
+config XEON_SP_COMMON_BASE
 	bool
+
+config SOC_INTEL_SKYLAKE_SP
+	bool
+	select XEON_SP_COMMON_BASE
 	help
-	  Intel Xeon SP support
+	  Intel Skylake-SP support
 
-if SOC_INTEL_XEON_SP
+if XEON_SP_COMMON_BASE
 
-config CPU_SPECIFIC_OPTIONS
+config	CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_RAMSTAGE_X86_32
@@ -54,6 +60,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select MICROCODE_BLOB_NOT_HOOKED_UP
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+	select FSP_CAR
 
 config MAINBOARD_USES_FSP2_0
 	  bool
@@ -67,11 +74,6 @@ config USE_FSP2_0_DRIVER
 	  select POSTCAR_CONSOLE
 	  select POSTCAR_STAGE
 
-config FSP_HEADER_PATH
-	  string "Location of FSP headers"
-	  depends on MAINBOARD_USES_FSP2_0
-	  default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp"
-
 config MAX_SOCKET
 	int
 	default 2
@@ -88,14 +90,6 @@ config PCR_BASE_ADDRESS
 	help
 	  This option allows you to select MMIO Base Address of sideband bus.
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xfe800000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x200000
-
 config DCACHE_BSP_STACK_SIZE
 	hex
 	default 0x10000
@@ -104,14 +98,6 @@ config MMCONF_BASE_ADDRESS
 	hex
 	default 0x80000000
 
-config CPU_MICROCODE_CBFS_LOC
-	hex
-	default 0xfff0fdc0
-
-config CPU_MICROCODE_CBFS_LEN
-	hex
-	default 0x7C00
-
 config C_ENV_BOOTBLOCK_SIZE
 	hex
 	default 0xC000
@@ -120,5 +106,4 @@ config HEAP_SIZE
 	hex
 	default 0x80000
 
-
 endif ## SOC_INTEL_XEON_SP

src/soc/intel/xeon_sp/Makefile.inc

@@ -13,46 +13,16 @@
 ## GNU General Public License for more details.
 ##
 
-ifeq ($(CONFIG_SOC_INTEL_XEON_SP),y)
+ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
 
-subdirs-y += ../../../cpu/intel/microcode
-subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
-subdirs-y += ../../../cpu/x86/tsc
-subdirs-y += ../../../cpu/x86/cache
-subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
+subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx
 
-bootblock-y += bootblock/bootblock.c
-bootblock-y += lpc.c
-bootblock-y += spi.c
-
-postcar-y += soc_util.c
+bootblock-y += bootblock.c spi.c lpc.c
+romstage-y += romstage.c reset.c util.c spi.c
+ramstage-y += uncore.c reset.c util.c lpc.c spi.c
 postcar-y += spi.c
 
-romstage-y += soc_util.c
-romstage-y += reset.c
-romstage-y += romstage.c
-romstage-y += soc_util.c
-romstage-y += spi.c
-romstage-y += hob_display.c
-romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
-romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
-
-ramstage-y += soc_util.c
-ramstage-y += uncore.c
-ramstage-y += reset.c
-ramstage-y += chip.c
-ramstage-y += soc_util.c
-ramstage-y += lpc.c
-ramstage-y += cpu.c
-ramstage-y += spi.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
-ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
-ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
-ramstage-y += hob_display.c
-
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include
 CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
 
-endif ## CONFIG_SOC_INTEL_XEON_SP
+endif ## XEON_SP_COMMON_BASE

src/soc/intel/xeon_sp/include/soc/util.h

@@ -13,13 +13,14 @@
  * GNU General Public License for more details.
  */
 
+#ifndef _XEON_SP_SOC_UTIL_H_
+#define _XEON_SP_SOC_UTIL_H_
 
-#ifndef _SOC_UTIL_H_
-#define _SOC_UTIL_H_
+#include <console/console.h>
 
-#include <hob_iiouds.h>
-#include <hob_memmap.h>
-#include <arch/acpi.h>
+void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3);
+void unlock_pam_regions(void);
+void get_stack_busnos(uint32_t *bus);
 
 #define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \
 	printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \
@@ -46,34 +47,4 @@
 #define FUNC_EXIT() \
 	printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__)
 
-struct iiostack_resource {
-	uint8_t     no_of_stacks;
-	STACK_RES   res[CONFIG_MAX_SOCKET * MAX_IIO_STACK];
-};
-
-uintptr_t get_tolm(uint32_t bus);
-void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit);
-uintptr_t get_cha_mmcfg_base(uint32_t bus);
-uint32_t top_of_32bit_ram(void); // Top of 32bit usable memory
-
-uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset);
-
-void get_stack_busnos(uint32_t *bus);
-void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3);
-uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack);
-void get_iiostack_info(struct iiostack_resource *info);
-
-int get_threads_per_package(void);
-int get_platform_thread_count(void);
-void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits);
-
-unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem);
-void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits,
-	uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread);
-
-void unlock_pam_regions(void);
-void xeonsp_init_cpu_config(void);
-void set_bios_init_completion(void);
-void config_reset_cpl3_csrs(void);
-
-#endif /* _SOC_UTIL_H_ */
+#endif

src/soc/intel/xeon_sp/lpc.c

@@ -17,11 +17,10 @@
 #include <arch/ioapic.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
-#include <soc/soc_util.h>
 #include <soc/iomap.h>
 #include <soc/pcr_ids.h>
 
-#include "chip.h"
+#include <chip.h>
 
 static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = {
 	{ 0, 0 }

src/soc/intel/xeon_sp/romstage.c

@@ -18,9 +18,9 @@
 #include <intelblocks/rtc.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
+#include <fsp/util.h>
 #include <soc/romstage.h>
-#include <soc/soc_util.h>
-#include "chip.h"
+#include <soc/util.h>
 
 asmlinkage void car_stage_entry(void)
 {
@@ -55,27 +55,3 @@ asmlinkage void car_stage_entry(void)
 
 	run_postcar_phase(&pcf);
 }
-
-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
-{
-}
-
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
-{
-	const config_t *config = config_of_soc();
-	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-
-	mupd->FspmUpdVersion = FSP_UPD_VERSION;
-
-	// ErrorLevel - 0 (disable) to 8 (verbose)
-	m_cfg->PcdFspMrcDebugPrintErrorLevel = 0;
-	m_cfg->PcdFspKtiDebugPrintErrorLevel = 0;
-
-	soc_memory_init_params(m_cfg);
-
-	mainboard_memory_init_params(mupd);
-
-	m_cfg->VTdConfig.VTdSupport = config->vtd_support;
-	m_cfg->VTdConfig.CoherencySupport = config->coherency_support;
-	m_cfg->VTdConfig.ATS = config->ats_support;
-}

src/soc/intel/xeon_sp/skx/Kconfig

@@ -0,0 +1,69 @@
+##
+## SPDX-License-Identifier: GPL-2.0-only
+## This file is part of the coreboot project.
+##
+
+if SOC_INTEL_SKYLAKE_SP
+
+config MAINBOARD_USES_FSP2_0
+	  bool
+	  default y
+
+config USE_FSP2_0_DRIVER
+	  def_bool y
+	  depends on MAINBOARD_USES_FSP2_0
+	  select PLATFORM_USES_FSP2_0
+	  select UDK_2015_BINDING
+	  select POSTCAR_CONSOLE
+	  select POSTCAR_STAGE
+
+config FSP_HEADER_PATH
+	  string "Location of FSP headers"
+	  depends on MAINBOARD_USES_FSP2_0
+	  default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp"
+
+config MAX_SOCKET
+	int
+	default 2
+
+# For 2S config, the number of cpus could be as high as
+# 2 threads * 20 cores * 2 sockets
+config MAX_CPUS
+	int
+	default 80
+
+config PCR_BASE_ADDRESS
+	hex
+	default 0xfd000000
+	help
+	  This option allows you to select MMIO Base Address of sideband bus.
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xfe800000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x200000
+
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x10000
+
+config CPU_MICROCODE_CBFS_LOC
+	hex
+	default 0xfff0fdc0
+
+config CPU_MICROCODE_CBFS_LEN
+	hex
+	default 0x7C00
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0xC000
+
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+endif

src/soc/intel/xeon_sp/skx/Makefile.inc

@@ -0,0 +1,36 @@
+##
+## SPDX-License-Identifier: GPL-2.0-only
+## This file is part of the coreboot project.
+##
+
+ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y)
+
+subdirs-y += ../../../../cpu/intel/microcode
+subdirs-y += ../../../../cpu/intel/turbo
+subdirs-y += ../../../../cpu/x86/lapic
+subdirs-y += ../../../../cpu/x86/mtrr
+subdirs-y += ../../../../cpu/x86/tsc
+subdirs-y += ../../../../cpu/x86/cache
+subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
+
+postcar-y += soc_util.c
+
+romstage-y += soc_util.c
+romstage-y += romstage.c
+romstage-y += soc_util.c
+romstage-y += hob_display.c
+romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
+romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
+
+ramstage-y += soc_util.c
+ramstage-y += chip.c
+ramstage-y += soc_util.c
+ramstage-y += cpu.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
+ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
+ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
+ramstage-y += hob_display.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx
+
+endif ## CONFIG_SOC_INTEL_SKYLAKE_SP

src/soc/intel/xeon_sp/skx/acpi.c

@@ -880,7 +880,7 @@ unsigned long northbridge_write_acpi_tables(struct device *device,
 	acpi_slit_t *slit;
 	acpi_dmar_t *dmar;
 
-	const struct soc_intel_xeon_sp_config *const config = config_of(device);
+	const struct soc_intel_xeon_sp_skx_config *const config = config_of(device);
 
 	/* SRAT */
 	current = ALIGN(current, 8);

src/soc/intel/xeon_sp/skx/chip.c

@@ -589,8 +589,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	mainboard_silicon_init_params(silupd);
 }
 
-struct chip_operations soc_intel_xeon_sp_ops = {
-	CHIP_NAME("Intel Xeon-SP SOC")
+struct chip_operations soc_intel_xeon_sp_skx_ops = {
+	CHIP_NAME("Intel Skylake-SP")
 	.enable_dev = soc_enable_dev,
 	.init = soc_init,
 	.final = soc_final

src/soc/intel/xeon_sp/skx/chip.h

@@ -21,7 +21,7 @@
 #include <intelblocks/cfg.h>
 #include <soc/irq.h>
 
-struct soc_intel_xeon_sp_config {
+struct soc_intel_xeon_sp_skx_config {
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
 
@@ -86,6 +86,6 @@ struct soc_intel_xeon_sp_config {
 
 extern struct chip_operations soc_intel_xeon_sp_ops;
 
-typedef struct soc_intel_xeon_sp_config config_t;
+typedef struct soc_intel_xeon_sp_skx_config config_t;
 
 #endif

src/soc/intel/xeon_sp/skx/include/soc/soc_util.h

@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef _SOC_UTIL_H_
+#define _SOC_UTIL_H_
+
+#include <hob_iiouds.h>
+#include <hob_memmap.h>
+#include <arch/acpi.h>
+#include <soc/util.h>
+
+struct iiostack_resource {
+	uint8_t     no_of_stacks;
+	STACK_RES   res[CONFIG_MAX_SOCKET * MAX_IIO_STACK];
+};
+
+uintptr_t get_tolm(uint32_t bus);
+void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit);
+uintptr_t get_cha_mmcfg_base(uint32_t bus);
+uint32_t top_of_32bit_ram(void); // Top of 32bit usable memory
+
+uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset);
+
+uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack);
+void get_iiostack_info(struct iiostack_resource *info);
+
+int get_threads_per_package(void);
+int get_platform_thread_count(void);
+void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits);
+
+unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem);
+void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits,
+	uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread);
+
+void xeonsp_init_cpu_config(void);
+void set_bios_init_completion(void);
+void config_reset_cpl3_csrs(void);
+
+#endif /* _SOC_UTIL_H_ */

src/soc/intel/xeon_sp/skx/romstage.c

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <arch/romstage.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <intelblocks/rtc.h>
+#include <soc/romstage.h>
+#include <soc/soc_util.h>
+
+#include "chip.h"
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+	const config_t *config = config_of_soc();
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+	mupd->FspmUpdVersion = FSP_UPD_VERSION;
+
+	// ErrorLevel - 0 (disable) to 8 (verbose)
+	m_cfg->PcdFspMrcDebugPrintErrorLevel = 0;
+	m_cfg->PcdFspKtiDebugPrintErrorLevel = 0;
+
+	mainboard_memory_init_params(mupd);
+
+	m_cfg->VTdConfig.VTdSupport = config->vtd_support;
+	m_cfg->VTdConfig.CoherencySupport = config->coherency_support;
+	m_cfg->VTdConfig.ATS = config->ats_support;
+}

src/soc/intel/xeon_sp/skx/soc_util.c

@@ -30,6 +30,7 @@
 #include <soc/pcr_ids.h>
 #include <soc/soc_util.h>
 #include <stdlib.h>
+#include <soc/util.h>
 #include <timer.h>
 
 /*
@@ -69,24 +70,6 @@ uintptr_t get_cha_mmcfg_base(uint32_t bus)
 	return addr;
 }
 
-/*
- * Get Socket 0 CPUBUSNO(0), CPUBUSNO(1) PCI bus numbers UBOX (B0:D8:F2:Offset_CCh)
- * TODO: D0h
- */
-void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3)
-{
-	uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV,
-		UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR);
-	if (bus0)
-		*bus0 = (bus & 0xff);
-	if (bus1)
-		*bus1 = (bus >> 8) & 0xff;
-	if (bus2)
-		*bus2 = (bus >> 16) & 0xff;
-	if (bus3)
-		*bus3 = (bus >> 24) & 0xff;
-}
-
 uint32_t top_of_32bit_ram(void)
 {
 	uintptr_t mmcfg, tolm;
@@ -153,42 +136,6 @@ uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
 	return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack];
 }
 
-/* bus needs to be of size 6 (MAX_IIO_STACK) */
-void get_stack_busnos(uint32_t *bus)
-{
-	uint32_t reg1, reg2;
-
-	reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC),
-		0xcc);
-	reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC),
-		0xd0);
-
-	for (int i = 0; i < 4; ++i)
-		bus[i] = ((reg1 >> (i * 8)) & 0xff);
-	for (int i = 0; i < 2; ++i)
-		bus[4+i] = ((reg2 >> (i * 8)) & 0xff);
-}
-
-void unlock_pam_regions(void)
-{
-	uint32_t bus1 = 0;
-	uint32_t pam0123_unlock_dram = 0x33333330;
-	uint32_t pam456_unlock_dram = 0x00333333;
-
-	get_cpubusnos(NULL, &bus1, NULL, NULL);
-	pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
-		SAD_ALL_PAM0123_CSR, pam0123_unlock_dram);
-	pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
-		SAD_ALL_PAM456_CSR, pam456_unlock_dram);
-
-	uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
-		SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR);
-	uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
-		SAD_ALL_FUNC), SAD_ALL_PAM456_CSR);
-	printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n",
-		__FILE__, __func__, reg1, reg2);
-}
-
 /* return 1 if command timed out else 0 */
 static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask,
 	uint32_t target)

src/soc/intel/xeon_sp/uncore.c

@@ -21,7 +21,8 @@
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
-#include <soc/soc_util.h>
+#include <soc/util.h>
+#include <fsp/util.h>
 
 struct map_entry {
 	uint32_t    reg;

src/soc/intel/xeon_sp/util.c

@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <soc/pci_devs.h>
+#include <soc/util.h>
+
+void get_stack_busnos(uint32_t *bus)
+{
+	uint32_t reg1, reg2;
+
+	reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC),
+		0xcc);
+	reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC),
+		0xd0);
+
+	for (int i = 0; i < 4; ++i)
+		bus[i] = ((reg1 >> (i * 8)) & 0xff);
+	for (int i = 0; i < 2; ++i)
+		bus[4+i] = ((reg2 >> (i * 8)) & 0xff);
+}
+
+void unlock_pam_regions(void)
+{
+	uint32_t bus1 = 0;
+	uint32_t pam0123_unlock_dram = 0x33333330;
+	uint32_t pam456_unlock_dram = 0x00333333;
+
+	get_cpubusnos(NULL, &bus1, NULL, NULL);
+	pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
+		SAD_ALL_PAM0123_CSR, pam0123_unlock_dram);
+	pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
+		SAD_ALL_PAM456_CSR, pam456_unlock_dram);
+
+	uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
+		SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR);
+	uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
+		SAD_ALL_FUNC), SAD_ALL_PAM456_CSR);
+	printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n",
+		__FILE__, __func__, reg1, reg2);
+}
+
+void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3)
+{
+	uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV,
+		UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR);
+	if (bus0)
+		*bus0 = (bus & 0xff);
+	if (bus1)
+		*bus1 = (bus >> 8) & 0xff;
+	if (bus2)
+		*bus2 = (bus >> 16) & 0xff;
+	if (bus3)
+		*bus3 = (bus >> 24) & 0xff;
+}