GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() 

Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL,
which was deprecated in favor of a public PCI register (though only the
bits to enable debug port became public) 0x90. Therefore code needs to be
updated.

BUG=b:69231009
TEST=Build and boot grunt.

Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Richard Spiegel 2018-08-24 16:48:20 -07:00 committed by Martin Roth
parent 8120759d90
commit 6635b3d9a1
2 changed files with 12 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/soc/amd/stoneyridge/enable_usbdebug.c
View File

@ -22,8 +22,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
#define DEBUGPORT_MISC_CONTROL 0x80
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{ {
/* Enable all of the USB controllers */ /* Enable all of the USB controllers */
@ -40,13 +38,12 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{ {
u8 *base_regs = pci_ehci_base_regs(dev); u32 reg32, value;
u32 reg32;
/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ value = (port & 0x3) << DEBUG_PORT_SELECT_SHIFT;
reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); value |= DEBUG_PORT_ENABLE;
reg32 &= ~(0xf << 28); reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4);
reg32 |= (port << 28); reg32 &= ~DEBUG_PORT_MASK;
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ reg32 |= value;
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32);
} }

5
src/soc/amd/stoneyridge/include/soc/southbridge.h
View File

@ -305,6 +305,11 @@
#define OC_PORT2_SHIFT 8 #define OC_PORT2_SHIFT 8
#define OC_PORT3_SHIFT 12 #define OC_PORT3_SHIFT 12
#define EHCI_HUB_CONFIG4 0x90
#define DEBUG_PORT_SELECT_SHIFT 16
#define DEBUG_PORT_ENABLE BIT(18)
#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18))
#define WIDEIO_RANGE_ERROR -1 #define WIDEIO_RANGE_ERROR -1
#define TOTAL_WIDEIO_PORTS 3 #define TOTAL_WIDEIO_PORTS 3