mediatek/mt8183: Add I2C driver code
This patch implements i2c driver for MT8183. BUG=b:80501386 BRANCH=none TEST=Boot correctly on kukui. Change-Id: I0a4d78b494819f45951f78e5a618021000cf3463 Signed-off-by: Qii Wang <qii.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30976 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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02547c5886
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@ -6,6 +6,7 @@ bootblock-y += ../common/gpio.c gpio.c
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bootblock-y += ../common/pll.c pll.c
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bootblock-y += ../common/pll.c pll.c
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bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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bootblock-y += mt8183.c
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bootblock-y += mt8183.c
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bootblock-y += ../common/i2c.c i2c.c
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bootblock-y += ../common/timer.c
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bootblock-y += ../common/timer.c
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bootblock-y += ../common/uart.c
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bootblock-y += ../common/uart.c
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bootblock-y += ../common/wdt.c
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bootblock-y += ../common/wdt.c
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@ -18,6 +19,7 @@ verstage-y += auxadc.c
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verstage-y += ../common/gpio.c gpio.c
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verstage-y += ../common/gpio.c gpio.c
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verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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verstage-y += mt8183.c
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verstage-y += mt8183.c
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verstage-y += ../common/i2c.c i2c.c
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verstage-y += ../common/timer.c
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verstage-y += ../common/timer.c
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verstage-y += ../common/uart.c
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verstage-y += ../common/uart.c
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verstage-y += ../common/wdt.c
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verstage-y += ../common/wdt.c
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@ -36,6 +38,7 @@ romstage-y += ../common/pll.c pll.c
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romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c
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romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c
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romstage-y += ../common/rtc.c rtc.c
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romstage-y += ../common/rtc.c rtc.c
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romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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romstage-y += ../common/i2c.c i2c.c
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romstage-y += ../common/timer.c
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romstage-y += ../common/timer.c
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romstage-y += ../common/uart.c
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romstage-y += ../common/uart.c
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romstage-y += ../common/wdt.c
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romstage-y += ../common/wdt.c
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@ -43,6 +46,7 @@ romstage-y += ../common/wdt.c
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ramstage-y += auxadc.c
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ramstage-y += auxadc.c
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ramstage-y += ../common/cbmem.c emi.c
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ramstage-y += ../common/cbmem.c emi.c
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ramstage-y += ../common/gpio.c gpio.c
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ramstage-y += ../common/gpio.c gpio.c
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ramstage-y += ../common/i2c.c i2c.c
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ramstage-y += ../common/mmu_operations.c mmu_operations.c
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ramstage-y += ../common/mmu_operations.c mmu_operations.c
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ramstage-y += ../common/mtcmos.c mtcmos.c
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ramstage-y += ../common/mtcmos.c mtcmos.c
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ramstage-y += ../common/pmic_wrap.c
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ramstage-y += ../common/pmic_wrap.c
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@ -0,0 +1,150 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <device/mmio.h>
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#include <soc/pll.h>
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#include <soc/i2c.h>
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#include <soc/gpio.h>
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#define I2C_CLK_HZ (UNIVPLL_HZ / 20)
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struct mtk_i2c mtk_i2c_bus_controller[] = {
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/* i2c0 setting */
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{
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.i2c_regs = (void *)(I2C_BASE + 0x2000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE),
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},
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/* i2c1 setting */
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{
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.i2c_regs = (void *)(I2C_BASE + 0xc000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x400),
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},
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/* i2c2 setting */
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{
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.i2c_regs = (void *)(I2C_BASE + 0x4000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x200),
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},
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/* i2c3 setting */
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{
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.i2c_regs = (void *)(I2C_BASE + 0xa000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x380),
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},
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/* i2c4 setting */
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{
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.i2c_regs = (void *)(I2C_BASE + 0x3000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x80),
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},
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/* i2c5 setting */
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{
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.i2c_regs = (void *)(I2C_BASE + 0x11000),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480),
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},
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/* i2c6 setting */
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{
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.i2c_regs = (void *)(I2C_BASE),
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.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580),
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},
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};
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#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller)
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struct pad_func {
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gpio_t gpio;
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u8 func;
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};
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#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func}
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static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
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{
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PAD_FUNC(SDA0, SDA0),
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PAD_FUNC(SCL0, SCL0),
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},
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{
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PAD_FUNC(SDA1, SDA1),
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PAD_FUNC(SCL1, SCL1),
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},
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{
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PAD_FUNC(SDA2, SDA2),
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PAD_FUNC(SCL2, SCL2),
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},
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{
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PAD_FUNC(SDA3, SDA3),
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PAD_FUNC(SCL3, SCL3),
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},
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{
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PAD_FUNC(SDA4, SDA4),
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PAD_FUNC(SCL4, SCL4),
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},
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{
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PAD_FUNC(SDA5, SDA5),
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PAD_FUNC(SCL5, SCL5),
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},
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{
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PAD_FUNC(SDA6, SDA6),
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PAD_FUNC(SCL6, SCL6),
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},
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};
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static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
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{
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assert(bus < I2C_BUS_NUMBER);
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const struct pad_func *ptr = i2c_funcs[bus];
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for (size_t i = 0; i < 2; i++) {
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gpio_set_mode(ptr[i].gpio, ptr[i].func);
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gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP);
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}
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}
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static void mtk_i2c_speed_init(uint8_t bus)
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{
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uint8_t step_div;
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const uint8_t clock_div = 5;
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const uint8_t sample_div = 1;
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uint32_t i2c_freq;
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assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller));
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/* Calculate i2c frequency */
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step_div = DIV_ROUND_UP(I2C_CLK_HZ,
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(400 * KHz * sample_div * 2) * clock_div);
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i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div);
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assert(sample_div < 8 && step_div < 64 && i2c_freq <= 400 * KHz &&
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i2c_freq >= 380 * KHz);
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/* Init i2c bus Timing register */
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write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing,
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(sample_div - 1) << 8 | (step_div - 1));
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write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming,
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(sample_div - 1) << 6 | (step_div - 1));
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/* Init i2c bus clock_div register */
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write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div,
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clock_div - 1);
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}
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void mtk_i2c_bus_init(uint8_t bus)
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{
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mtk_i2c_speed_init(bus);
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mtk_i2c_set_gpio_pinmux(bus);
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}
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@ -36,8 +36,10 @@ enum {
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DRAMC_CH_BASE = IO_PHYS + 0x00228000,
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DRAMC_CH_BASE = IO_PHYS + 0x00228000,
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SSPM_SRAM_BASE = IO_PHYS + 0x00400000,
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SSPM_SRAM_BASE = IO_PHYS + 0x00400000,
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SSPM_CFG_BASE = IO_PHYS + 0x00440000,
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SSPM_CFG_BASE = IO_PHYS + 0x00440000,
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I2C_DMA_BASE = IO_PHYS + 0x01000080,
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AUXADC_BASE = IO_PHYS + 0x01001000,
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AUXADC_BASE = IO_PHYS + 0x01001000,
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UART0_BASE = IO_PHYS + 0x01002000,
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UART0_BASE = IO_PHYS + 0x01002000,
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I2C_BASE = IO_PHYS + 0x01005000,
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SPI0_BASE = IO_PHYS + 0x0100A000,
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SPI0_BASE = IO_PHYS + 0x0100A000,
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SPI1_BASE = IO_PHYS + 0x01010000,
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SPI1_BASE = IO_PHYS + 0x01010000,
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SPI2_BASE = IO_PHYS + 0x01012000,
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SPI2_BASE = IO_PHYS + 0x01012000,
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@ -0,0 +1,59 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_MEDIATEK_MT8183_I2C_H
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#define SOC_MEDIATEK_MT8183_I2C_H
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#include <soc/i2c_common.h>
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/* I2C Register */
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struct mt_i2c_regs {
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uint32_t data_port;
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uint32_t slave_addr;
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uint32_t intr_mask;
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uint32_t intr_stat;
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uint32_t control;
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uint32_t transfer_len;
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uint32_t transac_len;
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uint32_t delay_len;
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uint32_t timing;
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uint32_t start;
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uint32_t ext_conf;
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uint32_t ltiming;
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uint32_t hs;
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uint32_t io_config;
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uint32_t fifo_addr_clr;
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uint32_t reserved0[2];
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uint32_t transfer_aux_len;
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uint32_t clock_div;
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uint32_t time_out;
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uint32_t softreset;
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uint32_t reserved1[36];
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uint32_t debug_stat;
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uint32_t debug_ctrl;
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uint32_t reserved2[2];
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uint32_t fifo_stat;
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uint32_t fifo_thresh;
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uint32_t reserved3[932];
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uint32_t multi_dma;
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uint32_t reserved4[2];
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uint32_t rollback;
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};
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check_member(mt_i2c_regs, multi_dma, 0xf8c);
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void mtk_i2c_bus_init(uint8_t bus);
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#endif /* SOC_MEDIATEK_MT8183_I2C_H */
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@ -15,8 +15,10 @@
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#include <soc/mt8183.h>
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#include <soc/mt8183.h>
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#include <soc/wdt.h>
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#include <soc/wdt.h>
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#include <soc/gpio.h>
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void mt8183_early_init(void)
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void mt8183_early_init(void)
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{
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{
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mtk_wdt_init();
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mtk_wdt_init();
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gpio_set_i2c_eh_rsel();
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}
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}
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