From 66538e08770794b4bf7baadc53f167a405b870bc Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 5 May 2021 14:46:14 +0200 Subject: [PATCH] cpu/intel/socket_p: Increase DCACHE_RAM_SIZE The lowest bound for L2 cache size on Socket P is 512 KiB. This allows the use of cbfs mcache on all platforms. This fixes building when some debug options are enabled. Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/cpu/intel/socket_p/Kconfig | 2 +- src/mainboard/lenovo/t400/Kconfig | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index 4b99acead2..552ed7088c 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -12,7 +12,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex - default 0x8000 + default 0x10000 config DCACHE_BSP_STACK_SIZE hex diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 74977eba92..8c53a686e5 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500 select INTEL_GMA_HAVE_VBT - select NO_CBFS_MCACHE config VBOOT select VBOOT_VBNV_CMOS