soc/amd/mendocino: enable CPPC feature

This is sort-of reverts commit cbf290c692 ("soc/amd/sabrina: drop
CPPC code"), since it turned out that the CPPC feature is supported
on Sabrina (now Mendocino) despite this being missing from the
documentation I looked at when writing the patch referenced above.
Since the CPPC ACPI code generation functionality has been moved to
common code, this isn't a direct revert.

BUG=b:237336330
TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1c059653eeae207d723c77e8a78b19c86e362296
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

src/soc/amd/mendocino/Kconfig

@@ -53,6 +53,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_ACPI	# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_ACPI_ALIB	# TODO: Check if this is still correct
+	select SOC_AMD_COMMON_BLOCK_ACPI_CPPC
 	select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
 	select SOC_AMD_COMMON_BLOCK_ACPI_IVRS	# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_AOAC
@@ -82,6 +83,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H	# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_UART
 	select SOC_AMD_COMMON_BLOCK_UCODE
+	select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
 	select SOC_AMD_COMMON_FSP_DMI_TABLES	# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_FSP_PCI		# TODO: Check if this is still correct
 	select SSE2

src/soc/amd/mendocino/acpi.c

@@ -7,6 +7,7 @@
 #include <acpi/acpi.h>
 #include <acpi/acpigen.h>
 #include <amdblocks/acpi.h>
+#include <amdblocks/cppc.h>
 #include <amdblocks/cpu.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/ioapic.h>
@@ -358,6 +359,8 @@ void generate_cpu_entries(const struct device *device)
 		acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
 					  CSD_HW_ALL, 0);
 
+		generate_cppc_entries(cpu);
+
 		acpigen_pop_len();
 	}
 

src/soc/amd/mendocino/chip.h

@@ -69,6 +69,13 @@ struct soc_amd_mendocino_config {
 
 	uint8_t system_configuration;
 
+	uint8_t cppc_ctrl;
+	uint8_t cppc_perf_limit_max_range;
+	uint8_t cppc_perf_limit_min_range;
+	uint8_t cppc_epp_max_range;
+	uint8_t cppc_epp_min_range;
+	uint8_t cppc_preferred_cores;
+
 	/* telemetry settings */
 	uint32_t telemetry_vddcrvddfull_scale_current_mA;
 	uint32_t telemetry_vddcrvddoffset;

src/soc/amd/mendocino/fsp_m_params.c

@@ -122,6 +122,14 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	/* 0 is default */
 	mcfg->system_configuration = config->system_configuration;
 
+	/* when cppc_ctrl is 0 the other values won't be used */
+	mcfg->cppc_ctrl = config->cppc_ctrl;
+	mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range;
+	mcfg->cppc_perf_limit_min_range = config->cppc_perf_limit_min_range;
+	mcfg->cppc_epp_max_range = config->cppc_epp_max_range;
+	mcfg->cppc_epp_min_range = config->cppc_epp_min_range;
+	mcfg->cppc_preferred_cores = config->cppc_preferred_cores;
+
 	/* S0i3 enable */
 	mcfg->s0i3_enable = config->s0ix_enable;
 	mcfg->iommu_support = is_devfn_enabled(IOMMU_DEVFN);

src/soc/amd/mendocino/include/soc/msr.h

@@ -25,6 +25,21 @@
 #define  SERIAL_VID_DECODE_MICROVOLTS	5000
 #define  SERIAL_VID_BASE_MICROVOLTS	245000L
 
+#define MSR_CPPC_CAPABILITY_1				0xc00102b0
+#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
+#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF		16
+#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF	8
+#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF		0
+
+#define MSR_CPPC_ENABLE				0xc00102b1
+#define MSR_CPPC_REQUEST			0xc00102b3
+#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF	24
+#define SHIFT_CPPC_REQUEST_DES_PERF		16
+#define SHIFT_CPPC_REQUEST_MIN_PERF		8
+#define SHIFT_CPPC_REQUEST_MAX_PERF		0
+
+#define MSR_CPPC_STATUS		0xc00102b4
+
 #define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
 #define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8