soc/amd/cezanne: Init eSPI early if required
If the NO_EARLY_BOOTBLOCK_POSTCODES config option is enabled, configure eSPI as early as possible in the x86 boot sequence. We found that there are situations that can cause the system to hang if there are any port80h postcodes sent out before eSPI is initialized. BUG=b:191370340 TEST=Build & Boot with and without NO_EARLY_BOOTBLOCK_POSTCODES enabled. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0badb1c529e96ee4f81134287db53ce32473de6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55732 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -92,6 +92,12 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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set_caching();
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set_caching();
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write_resume_eip();
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write_resume_eip();
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enable_pci_mmconf();
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enable_pci_mmconf();
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/*
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* If NO_EARLY_BOOTBLOCK_POSTCODES is selected, we need to initialize port80h
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* routing as early as possible
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*/
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if (CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
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configure_port80_routing_early();
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/*
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/*
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* base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz
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* base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz
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@ -32,6 +32,13 @@ static void reset_i2c_peripherals(void)
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sb_reset_i2c_peripherals(&reset_info);
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sb_reset_i2c_peripherals(&reset_info);
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}
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}
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/* Initialize port80h routing early if needed */
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void configure_port80_routing_early(void)
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{
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if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
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espi_setup();
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}
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/* Before console init */
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/* Before console init */
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void fch_pre_init(void)
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void fch_pre_init(void)
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{
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{
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@ -69,6 +76,6 @@ void fch_early_init(void)
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if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
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if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
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lpc_disable_spi_rom_sharing();
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lpc_disable_spi_rom_sharing();
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if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
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if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
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espi_setup();
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espi_setup();
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}
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}
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@ -105,6 +105,7 @@
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#define I2C_PAD_CTRL_SPARE0 BIT(17)
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#define I2C_PAD_CTRL_SPARE0 BIT(17)
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#define I2C_PAD_CTRL_SPARE1 BIT(18)
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#define I2C_PAD_CTRL_SPARE1 BIT(18)
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void configure_port80_routing_early(void);
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void fch_pre_init(void);
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void fch_pre_init(void);
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void fch_early_init(void);
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void fch_early_init(void);
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void fch_init(void *chip_info);
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void fch_init(void *chip_info);
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