From 6670c689343505c23cbe073da84028802e286ea3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Sat, 6 Nov 2021 11:46:16 +0200
Subject: [PATCH] lippert/frontrunner-af: Fix PCI devices ASL
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There was a duplicate PCI 0:14.4 device in ASL. Only
keep one.

There are no PCI devices 0:2.0 or 0:3.0 on fam14 northbridge
for graphics. There are no PCIe root ports 0:9.0 or 0:a.0.

Change-Id: Ifa8abb851f8ae4863b2c6d52224d287fd272048d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 .../lippert/frontrunner-af/acpi/gpe.asl       |  1 -
 src/mainboard/lippert/frontrunner-af/dsdt.asl | 53 ++++---------------
 2 files changed, 11 insertions(+), 43 deletions(-)

diff --git a/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl b/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl
index 7472ffed71..5968ff3294 100644
--- a/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl
+++ b/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl
@@ -37,7 +37,6 @@
 
 		/*  GPIO0 or GEvent8 event  */
 		Method(_L18) {
-			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl
index 70a9b2e65d..48d8375dd6 100644
--- a/src/mainboard/lippert/frontrunner-af/dsdt.asl
+++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl
@@ -41,8 +41,6 @@ DefinitionBlock (
 
 	#include "acpi/routing.asl"
 
-	#include <southbridge/amd/cimx/sb800/acpi/pcie.asl>
-
 	/* Contains the supported sleep states for this chipset */
 	#include <southbridge/amd/common/acpi/sleepstates.asl>
 
@@ -109,17 +107,7 @@ DefinitionBlock (
 				}
 			}  /* end AGPB */
 
-			/* The external GFX bridge */
-			Device(PBR2) {
-				Name(_ADR, 0x00020000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PICM){ Return(APS2) }   /* APIC mode */
-					Return (PS2)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR2 */
-
-			/* Dev3 is also an external GFX bridge, not used in Herring */
+			/* Dev 2 & 3 are external GFX bridges, not used in Family14 */
 
 			Device(PBR4) {
 				Name(_ADR, 0x00040000)
@@ -158,25 +146,6 @@ DefinitionBlock (
 				} /* end _PRT */
 			} /* end PBR7 */
 
-			/* GPP */
-			Device(PBR9) {
-				Name(_ADR, 0x00090000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PICM){ Return(APS9) }   /* APIC mode */
-					Return (PS9)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR9 */
-
-			Device(PBRa) {
-				Name(_ADR, 0x000A0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PICM){ Return(APSA) }   /* APIC mode */
-					Return (PSA)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBRa */
-
 			Device(PE20) {
 				Name(_ADR, 0x00150000)
 				Name(_PRW, Package() {0x18, 4})
@@ -210,17 +179,11 @@ DefinitionBlock (
 				} /* end _PRT */
 			} /* end PE23 */
 
-			/* PCI slot 1, 2, 3 */
-			Device(PIBR) {
-				Name(_ADR, 0x00140004)
-				Name(_PRW, Package() {0x18, 4})
-
-				Method(_PRT, 0) {
-					Return (PCIB)
-				}
-			}
 
 			/* Describe the Southbridge devices */
+
+			#include <southbridge/amd/cimx/sb800/acpi/pcie.asl>
+
 			Device(STCR) {
 				Name(_ADR, 0x00110000)
 				#include "acpi/sata.asl"
@@ -351,8 +314,14 @@ DefinitionBlock (
 				#include "acpi/superio.asl"
 			} /* end LIBR */
 
-			Device(HPBR) {
+			/* PCI bridge */
+			Device(PIBR) {
 				Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
 			} /* end HostPciBr */
 
 			Device(ACAD) {