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mb/google/rex: Add WWAN poweron sequencing 

The PCIe WWAN module used on rex requires control over 4 signals to
successfully power it on. It is desirable to do this before passing
control to the payload, because the modem requires a ~10 seconds
initialization phase before it can be used.

The corrected sequence looks like:
1) Drive device into full reset and enable power in bootblock
2) Deassert FCPO in romstage, after power rails stabilize
3) Deassert WWAN_RST#, then WWAN_PERST# in ramstage

BUG=b:244077118
TEST=FM350 could be enumerated via lspci
Measured signals to check start-up Timing Sequence, tpr/ton1/ton2.
Tpr = 572mS
Ton1 = 6.3s
Ton2 = 6.3+4.17ms

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I6cda9348ef7f54efe5ba2358040596a1c2da1b13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67332
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ivy Jian 2022-09-05 11:30:48 +08:00 committed by Subrata Banik
parent d29b4aef1c
commit 66757b121a
1 changed files with 11 additions and 2 deletions
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13
src/mainboard/google/rex/variants/rex0/gpio.c
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@ -105,7 +105,7 @@ static const struct pad_config gpio_table_id0[] = {
/* GPP_C04 : [] ==> EN_WCAM_PWR */ /* GPP_C04 : [] ==> EN_WCAM_PWR */
PAD_CFG_GPO_LOCK(GPP_C04, 0, LOCK_CONFIG), PAD_CFG_GPO_LOCK(GPP_C04, 0, LOCK_CONFIG),
/* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */ /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */
PAD_CFG_GPO(GPP_C05, 0, PLTRST), PAD_CFG_GPO(GPP_C05, 1, PLTRST),
/* GPP_C06 : [] ==> USI_REPORT_EN */ /* GPP_C06 : [] ==> USI_REPORT_EN */
PAD_CFG_GPO(GPP_C06, 0, DEEP), PAD_CFG_GPO(GPP_C06, 0, DEEP),
/* GPP_C07 : [] ==> USI_INT */ /* GPP_C07 : [] ==> USI_INT */
@ -370,14 +370,21 @@ static const struct pad_config gpio_table_id0[] = {
/* Early pad configuration in bootblock */ /* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table_id0[] = { static const struct pad_config early_gpio_table_id0[] = {
/* GPP_B17 : [] ==> EN_WWAN_PWR */
PAD_CFG_GPO(GPP_B17, 1, DEEP),
/* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2),
/* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2),
/* GPP_C05 : [] ==> WWAN_PERST_L_STRAP (updated in ramstage) */
PAD_CFG_GPO(GPP_C05, 0, DEEP),
/* GPP_A15 : [] ==> WWAN_RST_L (updated in ramstage) */
PAD_CFG_GPO(GPP_A15, 0, DEEP),
/* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT),
/* GPP_E07 : [] ==> WWAN_FCPO_L (updated in romstage) */
PAD_CFG_GPO(GPP_E07, 0, DEEP),
/* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */
@ -414,6 +421,8 @@ static const struct pad_config default_early_gpio_table[] = {
static const struct pad_config romstage_gpio_table_id0[] = { static const struct pad_config romstage_gpio_table_id0[] = {
/* A20 : [] ==> SSD_PERST_L */ /* A20 : [] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_A20, 0, DEEP), PAD_CFG_GPO(GPP_A20, 0, DEEP),
/* GPP_E07 : [] ==> WWAN_FCPO_L */
PAD_CFG_GPO(GPP_E07, 1, DEEP),
}; };
const struct pad_config *variant_gpio_table(size_t *num) const struct pad_config *variant_gpio_table(size_t *num)