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mb/intel/tglrvp: sync up variant folders with latest up3 

During intial UP4 patch, below UP3 patches merged which should be
applied for UP4.
https://review.coreboot.org/c/coreboot/+/39201
https://review.coreboot.org/c/coreboot/+/39229
Merge these patches to UP4

BUG=none
BRANCH=none
TEST=Build TGL UP4

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
This commit is contained in:
Wonkyu Kim 2020-03-09 14:48:51 -07:00 committed by Patrick Georgi
parent 2bd2be545f
commit 66815114cf
2 changed files with 14 additions and 0 deletions
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1
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -48,6 +48,7 @@ chip soc/intel/tigerlake
# enabling EDP in PortA
register "DdiPortAConfig" = "1"
register "DdiPortBHpd" = "1"
register "DdiPort1Hpd" = "1"
register "DdiPort1Ddc" = "1"

13
src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
View File

@ -24,6 +24,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
/* Camera */
PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */
PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */
PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */
PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */
PAD_CFG_GPO(GPP_B23, 0, PLTRST),
PAD_CFG_GPO(GPP_C15, 0, PLTRST),
PAD_CFG_GPO(GPP_E22, 0, PLTRST),
@ -83,6 +87,15 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */
/* DP */
PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */
PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */
PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */
PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */
PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */
PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */
PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */
PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */
};
const struct pad_config *variant_gpio_table(size_t *num)