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usbdebug: Refactor early enable 

Always sanity check for EHCI class device and move
PCI function power enablement up.

Change-Id: I1eebe813fbb420738af2d572178213fc660f392a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2017-07-30 13:23:32 +03:00
parent d1a0c57708
commit 6683e409d3
13 changed files with 33 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/drivers/usb/pci_ehci.c
View File

@ -33,13 +33,17 @@ static struct device_operations ehci_dbg_ops;
int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
{
pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR);
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = dbg_dev;
#else
device_t dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev), PCI_DEV2DEVFN(dbg_dev));
#endif
u32 class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
if (class != PCI_EHCI_CLASSCODE)
return -1;
u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG);
if (!pos)
return -1;

5
src/include/device/pci_ehci.h
View File

@ -23,10 +23,13 @@
#define EHCI_BAR_INDEX 0x10
#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
/* Return PCI BDF for an EHCI controller by a given index. PCI function
* must already be powered to respond to configuration requests.
*/
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx);
u8 *pci_ehci_base_regs(pci_devfn_t dev);
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);
#ifndef __PRE_RAM__
#if !IS_ENABLED(CONFIG_USBDEBUG)

12
src/soc/amd/stoneyridge/enable_usbdebug.c
View File

@ -26,6 +26,10 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
if (hcd_idx == 3)
return PCI_DEV(0, 0x16, 0);
else if (hcd_idx == 2)
@ -46,11 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
}

13
src/soc/intel/broadwell/usb_debug.c
View File

@ -24,21 +24,10 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
u32 class;
pci_devfn_t dev = PCI_DEV(0, 0x1d, 0);
class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
if (class != PCI_EHCI_CLASSCODE)
return 0;
return dev;
return PCI_DEV(0, 0x1d, 0);
}
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
/* Hardcoded to physical port 1 */
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
}

12
src/southbridge/amd/agesa/hudson/enable_usbdebug.c
View File

@ -26,6 +26,10 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
if (hcd_idx == 3)
return PCI_DEV(0, 0x16, 2);
else if (hcd_idx == 2)
@ -46,11 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
}

12
src/southbridge/amd/pi/hudson/enable_usbdebug.c
View File

@ -26,6 +26,10 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
if (hcd_idx == 3)
return PCI_DEV(0, 0x16, 0);
else if (hcd_idx == 2)
@ -46,11 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
}

4
src/southbridge/amd/sb600/enable_usbdebug.c
View File

@ -32,7 +32,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
/* TODO: Allow changing the physical USB port used as Debug Port. */
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
}

4
src/southbridge/amd/sb700/enable_usbdebug.c
View File

@ -45,7 +45,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
}

12
src/southbridge/amd/sb800/enable_usbdebug.c
View File

@ -26,6 +26,10 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
if (hcd_idx == 3)
return PCI_DEV(0, 0x16, 2);
else if (hcd_idx == 2)
@ -46,11 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
}

22
src/southbridge/intel/common/usb_debug.c
View File

@ -27,27 +27,20 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
u32 class;
pci_devfn_t dev;
#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)
if (!IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS))
return PCI_DEV(0, 0x1d, 7);
if (hcd_idx==2)
dev = PCI_DEV(0, 0x1a, 0);
else
dev = PCI_DEV(0, 0x1d, 0);
#else
dev = PCI_DEV(0, 0x1d, 7);
#endif
class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)
if (class != PCI_EHCI_CLASSCODE) {
/* If we enter here before RCBA programming, EHCI function may
* appear with the highest function number instead.
*/
dev |= PCI_DEV(0, 0, 7);
class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
}
#endif
if (class != PCI_EHCI_CLASSCODE)
return 0;
dev |= PCI_DEV(0, 0, 7);
return dev;
}
@ -57,10 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
/* Bail out. No console to complain in. */
if (!dev)
return;
}

4
src/southbridge/nvidia/ck804/enable_usbdebug.c
View File

@ -41,7 +41,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
dword |= (port << 12);
pci_write_config32(dev, 0x74, dword);
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
}

4
src/southbridge/nvidia/mcp55/enable_usbdebug.c
View File

@ -41,7 +41,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
dword |= (port << 12);
pci_write_config32(dev, 0x74, dword);
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
}

4
src/southbridge/sis/sis966/enable_usbdebug.c
View File

@ -43,7 +43,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
dword |= (port << 12);
pci_write_config32(dev, 0x74, dword);
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
}