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This target is dead. 

The company is dead. 

It causes builds to fail, and that is not a problem we need to have. 

Removing it to remove the problems it causes. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2009-02-13 20:20:21 +00:00
parent 31197a61d9
commit 66948f7e8c
34 changed files with 0 additions and 7040 deletions
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460
src/mainboard/agami/aruma/Config.lb
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##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0
end
##
## Compute the start location and size size of
## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#needed by irq_tables and mptable and acpi_tables
#object get_bus_conf.o
if HAVE_ACPI_TABLES
object acpi_tables_static.o
object fadt.o
object dsdt.o
# makerule dsdt.c
# depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
# action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
# action "mv dsdt_lb.hex dsdt.c"
# end
# object ./dsdt.o
#
# makerule ssdt.c
# depends "$(MAINBOARD)/ssdt_lb_x.dsl"
# action "iasl -tc $(MAINBOARD)/ssdt_lb_x.dsl"
# action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt_lb_x.hex"
# action "mv ssdt_lb_x.hex ssdt.c"
# end
# object ./ssdt.o
#
# if ACPI_SSDTX_NUM
# makerule ssdt2.c
# depends "$(MAINBOARD)/dx/pci2.asl"
# action "iasl -tc $(MAINBOARD)/dx/pci2.asl"
# action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
# action "mv pci2.hex ssdt2.c"
# end
# object ./ssdt2.o
# makerule ssdt3.c
# depends "$(MAINBOARD)/dx/pci3.asl"
# action "iasl -tc $(MAINBOARD)/dx/pci3.asl"
# action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
# action "mv pci3.hex ssdt3.c"
# end
# object ./ssdt3.o
# makerule ssdt4.c
# depends "$(MAINBOARD)/dx/pci4.asl"
# action "iasl -tc $(MAINBOARD)/dx/pci4.asl"
# action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
# action "mv pci4.hex ssdt4.c"
# end
# object ./ssdt4.o
#
# end
end
#object reset.o
# FIXME: This should be solved generically.
#object vgabios.o
#driver atiragexl.o
if USE_DCACHE_RAM
if CONFIG_USE_INIT
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o cache_as_ram_auto.o"
end
else
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
else
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
else
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
##
## Include the secondary Configuration files
##
dir /pc80
config chip.h
# config for agami/aruma
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on end # device pci 18.0
device pci 18.0 on
# devices on link 1, link 1 == LDT 1
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end # 8131
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 off end
device pci 1.0 off end
#chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci 4.0 on end
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on
chip superio/winbond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x201
io 0x62 = 0x330
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on
chip drivers/i2c/i2cmux2 # pca9545 smbus mux
device i2c 71 on #pca9545 channel0
chip drivers/i2c/adm1026
device i2c 2d on end
end
end
device i2c 71 on #pca9545 channel1
chip drivers/generic/generic # fan board / pstray behind another mux
device i2c 2d on end
end
end
end
chip drivers/i2c/i2cmux2 # pca9543 smbus mux
device i2c 73 on #pca9543 channel0
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
end
device i2c 73 on #pca9543 channel1
chip drivers/generic/generic #dimm 1-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 1-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 1-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 1-1-1
device i2c 53 on end
end
end
end # chip end
chip drivers/generic/generic # ICS950405AF
device i2c 69 on end
end
end
device pci 1.5 off end
device pci 1.6 on end
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end # 8111
end # LDT1
device pci 18.0 on end # LDT2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end
chip northbridge/amd/amdk8
device pci 19.0 on end # LDT0
device pci 19.0 on end # LDT1
device pci 19.0 on # LDT2
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
end # LDT2
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
chip northbridge/amd/amdk8
device pci 1a.0 on end
device pci 1a.0 on end
device pci 1a.0 on # LDT2
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
end # LDT2
device pci 1a.1 on end
device pci 1a.2 on end
device pci 1a.3 on end
end
chip northbridge/amd/amdk8
device pci 1b.0 on end
device pci 1b.0 on # LDT1
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
end
device pci 1b.0 on end
device pci 1b.1 on end
device pci 1b.2 on end
device pci 1b.3 on end
end
end
end

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src/mainboard/agami/aruma/Options.lb
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uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES
uses ACPI_SSDTX_NUM
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CC
uses HOSTCC
uses CROSS_COMPILE
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_CHIP_NAME
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
uses CONFIG_USE_PRINTK_IN_CAR
uses SERIAL_CPU_INIT
uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID
uses HW_MEM_HOLE_SIZEK
uses CONFIG_PCI_64BIT_PREF_MEM
###
### Build options
###
##
## ROM_SIZE is the size of boot ROM that this board will use.
##
default ROM_SIZE=524288
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
# 256k
default FALLBACK_SIZE=0x40000
##
## Set this.
##
default CONFIG_CHIP_NAME=1
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
##
## Use hard_reset for rebooting, it uses reg. 0xcf9 in the amd8111.
##
default HAVE_HARD_RESET=1
##
## set memory hole size
##
default HW_MEM_HOLE_SIZEK=0x300000
#default HW_MEM_HOLE_SIZEK=0x200000
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=23
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
default HAVE_ACPI_TABLES=1
## extra SSDT num
default ACPI_SSDTX_NUM=3
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
##
## Build code for SMP support
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=8
default CONFIG_MAX_PHYSICAL_CPUS=4
default CONFIG_LOGICAL_CPUS=1
#default ALLOW_HT_OVERCLOCKING=1
default ENABLE_APIC_EXT_ID=1
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1 # SDE was 0
#HT Unit ID offset
#default HT_CHAIN_UNITID_BASE=0xa
#real SB Unit ID
#default HT_CHAIN_END_UNITID_BASE=0x6
#make the SB HT chain on bus 0
#default SB_HT_CHAIN_ON_BUS0=1
#allow capable device use that above 4G
#default CONFIG_PCI_64BIT_PREF_MEM=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcc000
default DCACHE_RAM_SIZE=0x4000
default CONFIG_USE_INIT=0
#default CONFIG_USE_INIT=1
default CONFIG_USE_PRINTK_IN_CAR=1
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="ARUMA"
default MAINBOARD_VENDOR="AGAMI"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x36c0
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
##
## Use a 32K heap
##
default HEAP_SIZE=0x8000
##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD = 1
###
### Defaults of options that you may want to override in the target config file
###
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##
## The Serial Console
##
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
#default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
##
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## CRIT 3 critical conditions
## ERR 4 error conditions
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## These values can be overwritten by corebootv2/targets/agami/aruma/Config.lb
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
#VGA
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
#default CONFIG_CONSOLE_VGA=0
#default CONFIG_PCI_ROM_RUN=0
### End Options.lb
end

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src/mainboard/agami/aruma/acpi_tables.c
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/*
* Agami Aruma ACPI support
*
* Copyright 2005 Stefan Reinauer
* Copyright 2005 AMD
*
* written by Stefan Reinauer <stepan@openbios.org>
* 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
*/
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <../../../northbridge/amd/amdk8/amdk8_acpi.h>
#define DUMP_ACPI_TABLES 0
#if DUMP_ACPI_TABLES == 1
static void dump_mem(unsigned start, unsigned end)
{
unsigned i;
print_debug("dump_mem:");
for (i = start; i < end; i++) {
if ((i & 0xf) == 0) {
printk_debug("\n%08x:", i);
}
printk_debug(" %02x",
(unsigned char) *((unsigned char *) i));
}
print_debug("\n");
}
#endif
#define HC_POSSIBLE_NUM 8
extern unsigned char AmlCode[];
#if ACPI_SSDTX_NUM >= 1
extern unsigned char AmlCode_ssdt2[];
extern unsigned char AmlCode_ssdt3[];
extern unsigned char AmlCode_ssdt4[];
//extern unsigned char AmlCode_ssdt5[];
//extern unsigned char AmlCode_ssdt6[];
//extern unsigned char AmlCode_ssdt7[];
//extern unsigned char AmlCode_ssdt8[];
#endif
#define IO_APIC_ADDR 0xfec00000UL
extern unsigned char bus_isa;
extern unsigned char bus_8111_0;
extern unsigned char bus_8111_1;
extern unsigned char bus_8131[7][3]; // another 6 8131
extern unsigned apicid_8111;
extern unsigned apicid_8131[7][2];
extern unsigned pci1234[];
extern unsigned hc_possible_num;
extern unsigned sblk;
extern unsigned sbdn;
extern unsigned hcdn[];
extern unsigned sbdnx[7]; // for all 8131
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
return current;
}
unsigned long acpi_fill_madt(unsigned long current)
{
unsigned int gsi_base = 0x18;
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write 8111 IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
apicid_8111, IO_APIC_ADDR, 0);
/* Write all 8131/8132 IOAPICs */
{
device_t dev;
struct resource *res;
dev = dev_find_slot(bus_8131[0][0], PCI_DEVFN(sbdnx[0], 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
apicid_8131[0][0], res->base, gsi_base);
gsi_base += 4;
}
}
dev = dev_find_slot(bus_8131[0][0], PCI_DEVFN(sbdnx[0] + 1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
apicid_8131[0][1], res->base, gsi_base);
gsi_base += 4;
}
}
}
int i;
for (i = 1; i < hc_possible_num; i++)
{ // 0: is hc sblink
device_t dev;
int j;
struct resource *res;
if ((pci1234[i] & 1) != 1)
continue;
j = (i - 1) * 2 + 1;
dev = dev_find_slot(bus_8131[j][0], PCI_DEVFN(sbdnx[j], 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
apicid_8131[j][0], res->base, gsi_base);
gsi_base += 4;
}
}
dev =
dev_find_slot(bus_8131[j][0],
PCI_DEVFN(sbdnx[j] + 1, 1));
if (dev)
{
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
apicid_8131[j][1], res->base, gsi_base);
gsi_base += 4;
}
}
dev =
dev_find_slot(bus_8131[j + 1][0],
PCI_DEVFN(sbdnx[j + 1], 1));
if (dev)
{
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
apicid_8131[j + 1][0], res->base, gsi_base);
gsi_base += 4;
}
}
dev = dev_find_slot(bus_8131[j + 1][0], PCI_DEVFN(sbdnx[j + 1] + 1, 1));
if (dev)
{
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
apicid_8131[j + 1][1], res->base, gsi_base);
gsi_base += 4;
}
}
}
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high */
/* create all subtables for processors */
current = acpi_create_madt_lapic_nmis(current, 5, 1);
/* 1: LINT1 connect to NMI */
return current;
}
unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) {
k8acpi_write_vars();
return (unsigned long) (acpigen_get_current());
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_srat_t *srat;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
acpi_header_t *ssdtx;
unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM];
int i;
/* Align ACPI tables to 16byte */
start = (start + 0x0f) & -0x10;
current = start;
printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *) start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt);
acpi_write_rsdt(rsdt);
get_bus_conf(); // get sblk, pci1234, and sbdn
/*
* We explicitly add these tables later on:
*/
printk_debug("ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdt, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
printk_debug("ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
acpi_add_table(rsdt, madt);
/* SRAT */
printk_debug("ACPI: * SRAT\n");
srat = (acpi_srat_t *) current;
acpi_create_srat(srat);
current += srat->header.length;
acpi_add_table(rsdt, srat);
/* SSDT */
printk_debug("ACPI: * SSDT\n");
ssdt = (acpi_header_t *)current;
acpi_create_ssdt_generator(ssdt, "DYNADATA");
current += ssdt->length;
acpi_add_table(rsdt, ssdt);
#if ACPI_SSDTX_NUM >= 1
// we need to make ssdt2 match to PCI2 in pci2.asl,... pci1234[1]
AmlCode_ssdtx[1] = AmlCode_ssdt2; // if you have different HT IO card for the same ht slot, here need to check vendor id, to set coresponding SSDT
AmlCode_ssdtx[2] = AmlCode_ssdt3;
AmlCode_ssdtx[3] = AmlCode_ssdt4;
// AmlCode_ssdtx[4] = AmlCode_ssdt5;
// AmlCode_ssdtx[5] = AmlCode_ssdt6;
// AmlCode_ssdtx[6] = AmlCode_ssdt7;
// AmlCode_ssdtx[7] = AmlCode_ssdt8;
//same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table
for (i = 1; i < hc_possible_num; i++) { // 0: is hc sblink
if ((pci1234[i] & 1) != 1)
continue;
printk_debug("ACPI: * SSDT for PCI%d\n", i + 1); //pci0 and pci1 are in dsdt
ssdtx = (acpi_header_t *) current;
current += ((acpi_header_t *) AmlCode_ssdtx[i])->length;
memcpy((void *) ssdtx, (void *) AmlCode_ssdtx[i],
((acpi_header_t *) AmlCode_ssdtx[i])->length);
acpi_add_table(rsdt, ssdtx);
}
#endif
/* FACS */
printk_debug("ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* DSDT */
printk_debug("ACPI: * DSDT\n");
dsdt = (acpi_header_t *) current;
current += ((acpi_header_t *) AmlCode)->length;
memcpy((void *) dsdt, (void *) AmlCode,
((acpi_header_t *) AmlCode)->length);
printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt,
dsdt->length);
/* FDAT */
printk_debug("ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdt, fadt);
#if DUMP_ACPI_TABLES == 1
printk_debug("rsdp\n");
dump_mem(rsdp, ((void *) rsdp) + sizeof(acpi_rsdp_t));
printk_debug("rsdt\n");
dump_mem(rsdt, ((void *) rsdt) + sizeof(acpi_rsdt_t));
printk_debug("madt\n");
dump_mem(madt, ((void *) madt) + madt->header.length);
printk_debug("srat\n");
dump_mem(srat, ((void *) srat) + srat->header.length);
printk_debug("ssdt\n");
dump_mem(ssdt, ((void *) ssdt) + ssdt->length);
printk_debug("fadt\n");
dump_mem(fadt, ((void *) fadt) + fadt->header.length);
#endif
printk_info("ACPI: done.\n");
return current;
}

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@ -1,252 +0,0 @@
/*
* Agami Aruma ACPI support
*
* written by Stefan Reinauer <stepan@coresystems.de>
* (C) 2005 Stefan Reinauer
* (C) 2007 coresystems GmbH
*/
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
#include <device/pci.h>
#include <device/pci_ids.h>
extern unsigned char AmlCode[];
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
return current;
}
#define IO_APIC_ADDR 0xfec00000UL
unsigned long acpi_fill_madt(unsigned long current)
{
unsigned int gsi_base=0x18, ioapic_nr=2, i;
device_t dev=0;
/* creare all subtables for 4p */
#ifdef PRE_REVE
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 17);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 18);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 19);
#endif
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 16);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 18);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 20);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 22);
/* Write 8111 IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 1,
IO_APIC_ADDR, 0);
/* Write the first 8131 IOAPICs */
for(i = 0; i < 2; i++) {
if (dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, dev)){
ACPI_WRITE_MADT_IOAPIC(dev, ioapic_nr);
ioapic_nr++;
}
}
/* Write the 8132 IOAPICs if they exist */
for(i = 0; i < 4; i++) {
if (dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7459, dev)){
ACPI_WRITE_MADT_IOAPIC(dev, ioapic_nr);
ioapic_nr++;
}
}
/* in the event there were no 8132s reset dev and look for the 8131s */
/* first skip the onboard 8131 */
dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, 0);
dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, dev);
/* Write all 8131 IOAPICs */
while((dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, dev))) {
ACPI_WRITE_MADT_IOAPIC(dev, ioapic_nr);
ioapic_nr++;
}
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
current, 1, 0, 2, 0 );
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
current, 1, 0, 2, 0 );
return current;
}
/* The next two tables are used by our DSDT and are freely defined
* here. This construct is used because the bus numbers containing
* the 8131 bridges may vary so that we need to pass coreboot
* knowledge into the DSDT
*/
typedef struct lnxc_busses {
u8 secondary;
u8 subordinate;
} acpi_lnxb_busses_t;
typedef struct acpi_lnxb {
struct acpi_table_header header;
acpi_lnxb_busses_t busses[5];
} acpi_lnxb_t;
/* special coreboot acpi table */
void acpi_create_lnxb(acpi_lnxb_t *lnxb)
{
device_t dev;
int busidx=0;
acpi_header_t *header=&(lnxb->header);
/* fill out header fields */
memcpy(header->signature, "LNXB", 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, "LNXBIOS ", 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->length = sizeof(acpi_lnxb_t);
header->revision = 1;
/*
* Write external 8131 bus ranges
*/
/* first skip the onboard 8131 */
dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, 0);
dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, dev);
/* now look at the last 8131 in each chain,
* as it contains the valid bus ranges
*/
/* Add a check for 8132 devices, device ID == 0x7458 */
while((dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7458, dev))
&& busidx<5 ) {
int subu, fn, slot;
acpi_lnxb_busses_t *busses;
if(PCI_SLOT(dev->path.u.pci.devfn)!=4)
continue;
busses=&(lnxb->busses[busidx]);
lnxb->busses[busidx].secondary = dev->bus->secondary;
lnxb->busses[busidx].subordinate =
pci_read_config8(dev, PCI_SUBORDINATE_BUS);
#if 0
/* SDE-test print out lnbx table values */
printk_info("ACPI: 7458 lnxb value, secondary %lx, subordinate %1x \n",
lnxb->busses[busidx].secondary, lnxb->busses[busidx].subordinate);
#endif
busidx++;
}
dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, 0);
dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, dev);
while((dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, dev))
&& busidx<5 ) {
int subu, fn, slot;
acpi_lnxb_busses_t *busses;
if(PCI_SLOT(dev->path.u.pci.devfn)!=4)
continue;
busses=&(lnxb->busses[busidx]);
lnxb->busses[busidx].secondary = dev->bus->secondary;
lnxb->busses[busidx].subordinate =
pci_read_config8(dev, PCI_SUBORDINATE_BUS);
#if 0
/* SDE-test print out lnbx table values */
printk_info("ACPI: 7450 lnxb value, secondary %lx, subordinate %1x \n",
lnxb->busses[busidx].secondary, lnxb->busses[busidx].subordinate);
#endif
busidx++;
}
header->checksum = acpi_checksum((void *)lnxb, sizeof(acpi_lnxb_t));
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_lnxb_t *lnxb;
acpi_header_t *dsdt;
/* Align ACPI tables to 16byte */
start = ( start + 0x0f ) & -0x10;
current = start;
printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt);
acpi_write_rsdt(rsdt);
/*
* We explicitly add these tables later on:
*/
printk_debug("ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdt,hpet);
/* If we want to use HPET Timers Linux wants an MADT */
printk_debug("ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current+=madt->header.length;
acpi_add_table(rsdt,madt);
printk_debug("ACPI: * LNXB\n");
lnxb=(acpi_lnxb_t *)current;
current += sizeof(acpi_facs_t);
acpi_create_lnxb(lnxb);
printk_debug("ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
dsdt = (acpi_header_t *)current;
current += ((acpi_header_t *)AmlCode)->length;
memcpy((void *)dsdt,(void *)AmlCode, \
((acpi_header_t *)AmlCode)->length);
/* fix up dsdt */
((u32 *)dsdt)[11]=((u32)lnxb)+sizeof(acpi_header_t);
/* recalculate checksum */
dsdt->checksum = 0;
dsdt->checksum = acpi_checksum(dsdt,dsdt->length);
printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
printk_debug("ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt,facs,dsdt);
acpi_add_table(rsdt,fadt);
printk_info("ACPI: done.\n");
return current;
}

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#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
#include <stdlib.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/amd/model_fxx_rev.h>
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
// pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
// outb(0x0e, 0x0cf9);
outb(0x06, 0x0cf9); /* this value will assert RESET_L and LDTRST_L */
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0),
SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0),
SMBUS_IO_BASE + 0xc0 + 29);
} else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0),
SMBUS_IO_BASE + 0xc0 + 29);
}
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0),
SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_SWITCH1 0x71
#define SMBUS_SWITCH2 0x73
/* Switch 1: pca 9545, Switch 2: pca 9543 */
unsigned device = (ctrl->channel0[0]) >> 8;
/* Disable all outputs on SMBus switch 1 */
smbus_send_byte(SMBUS_SWITCH1, 0x0);
/* Select SMBus switch 2 Channel 0/1 */
smbus_send_byte(SMBUS_SWITCH2, device);
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c"
#define CHAN0 0x100
#define CHAN1 0x200
#define NODE_RAM(x) \
.node_id = 0+x, \
.f0 = PCI_DEV(0, 0x18+x, 0), \
.f1 = PCI_DEV(0, 0x18+x, 1), \
.f2 = PCI_DEV(0, 0x18+x, 2), \
.f3 = PCI_DEV(0, 0x18+x, 3)
static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
{ NODE_RAM(0),
.channel0 = { (0xa0>>1)|CHAN0, (0xa4>>1)|CHAN0, 0, 0 },
.channel1 = { (0xa2>>1)|CHAN0, (0xa6>>1)|CHAN0, 0, 0 }
},
{ NODE_RAM(1),
.channel0 = { (0xa8>>1)|CHAN0, (0xac>>1)|CHAN0, 0, 0 },
.channel1 = { (0xaa>>1)|CHAN0, (0xae>>1)|CHAN0, 0, 0 }
},
{ NODE_RAM(2),
.channel0 = { (0xa8>>1)|CHAN1, (0xac>>1)|CHAN1, 0, 0 },
.channel1 = { (0xaa>>1)|CHAN1, (0xae>>1)|CHAN1, 0, 0 }
},
{ NODE_RAM(3),
.channel0 = { (0xa0>>1)|CHAN1, (0xa4>>1)|CHAN1, 0, 0 },
.channel1 = { (0xa2>>1)|CHAN1, (0xa6>>1)|CHAN1, 0, 0 }
}
};
int needs_reset;
if (bist == 0) {
k8_init_and_stop_secondaries();
}
/* Setup the console */
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_aruma_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset=ht_setup_chains_x();
#if 0
dump_pci_devices();
#endif
#if 0
print_pci_devices();
#endif
//#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0)
// if(read_option(CMOS_VSTART_amdk8_1GHz, CMOS_VLEN_amdk8_1GHz, 0))
// {
// print_debug("AMDK8 allowed at 1GHz\r\n");
// } else {
// print_debug("AMDK8 allowed at 800Hz only\r\n");
// }
// if(read_option(CMOS_VSTART_amd8131_800MHz, CMOS_VLEN_amd8131_800MHz, 0))
// {
// print_debug("AMD8131 allowed at 800MHz\r\n");
// } else {
// print_debug("AMD8131 allowed at 600Hz only\r\n");
// }
//#endif
if (needs_reset) {
print_info("HyperT reset -\r\n");
soft_reset();
}
enable_smbus();
memreset_setup();
sdram_initialize(ARRAY_SIZE(cpu), cpu);
#if 0
/* Check the first 1M */
ram_check(0x00000000, 0x000100000);
#endif
}

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#define ASSEMBLY 1
#define ASM_CONSOLE_LOGLEVEL 3
#define __ROMCC__
#define RAMINIT_SYSINFO 0
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
//use by raminit
#define QRANK_DIMM_SUPPORT 1
//used by incoherent_ht
//#define K8_SCAN_PCI_BUS 1
//#define K8_ALLOCATE_IO_RANGE 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
//outb(0x0e, 0x0cf9);
outb(0x06, 0x0cf9); /* this value will assert RESET_L and LDTRST_L */
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
//outb(0x0e, 0x0cf9);
outb(0x06, 0x0cf9); /* this value will assert RESET_L and LDTRST_L */
}
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static void memreset_setup(void)
{
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0),
SMBUS_IO_BASE + 0xc0 + 29);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0),
SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_SWITCH1 0x71
#define SMBUS_SWITCH2 0x73
/* Switch 1: pca 9545, Switch 2: pca 9543 */
unsigned device = (ctrl->channel0[0]) >> 8;
/* Disable all outputs on SMBus switch 1 */
smbus_send_byte(SMBUS_SWITCH1, 0x0);
/* Select SMBus switch 2 Channel 0/1 */
smbus_send_byte(SMBUS_SWITCH2, device);
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
/* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#define CHAN0 0x100
#define CHAN1 0x200
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#if USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the flash access */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// node 0
(0xa0>>1)|CHAN0, (0xa4>>1)|CHAN0, 0, 0,
(0xa2>>1)|CHAN0, (0xa6>>1)|CHAN0, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
// node 1
(0xa8>>1)|CHAN0, (0xac>>1)|CHAN0, 0, 0,
(0xaa>>1)|CHAN0, (0xae>>1)|CHAN0, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// node 2
(0xa8>>1)|CHAN1, (0xac>>1)|CHAN1, 0, 0,
(0xaa>>1)|CHAN1, (0xae>>1)|CHAN1, 0, 0,
// node 3
(0xa0>>1)|CHAN1, (0xa4>>1)|CHAN1, 0, 0,
(0xa2>>1)|CHAN1, (0xa6>>1)|CHAN1, 0, 0,
#endif
};
int needs_reset;
unsigned bsp_apicid = 0;
struct mem_controller ctrl[8];
unsigned nodes;
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_aruma_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
/* here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
wait_all_core0_started();
start_other_cores();
#endif
wait_all_aps_started(bsp_apicid);
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
nodes = get_nodes();
//It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
memreset_setup();
sdram_initialize(nodes, ctrl);
/* Reset SMBus switches to access the ADM1026 */
smbus_send_byte(SMBUS_SWITCH1, 0x0);
smbus_send_byte(SMBUS_SWITCH2, 0x0);
post_cache_as_ram();
}

4
src/mainboard/agami/aruma/chip.h
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@ -1,4 +0,0 @@
extern struct chip_operations mainboard_agami_aruma_ops;
struct mainboard_agami_aruma_config {
};

103
src/mainboard/agami/aruma/cmos.layout
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@ -1,103 +0,0 @@
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
#96 288 r 0 temporary_filler
0 384 r 0 reserved_memory
384 1 e 4 boot_option
385 1 e 4 last_boot
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 dual_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
420 4 e 7 boot_second
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Network
7 1 HDD
7 2 Floppy
7 8 Fallback_Network
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 DDR400
8 1 DDR333
8 2 DDR266
8 3 DDR200
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 983 984

1980
src/mainboard/agami/aruma/dsdt.c
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172
src/mainboard/agami/aruma/dx/amd8111.asl
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/*
* Copyright 2005 AMD
*/
//AMD8111
Name (APIC, Package (0x04)
{
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
})
Name (PICM, Package (0x04)
{
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00},
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00},
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00},
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00}
})
Name (DNCG, Ones)
Method (_PRT, 0, NotSerialized)
{
If (LEqual (^DNCG, Ones)) {
Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
// Update the Device Number according to SBDN
Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
Store (0x00, ^DNCG)
}
If (LNot (PICF)) {
Return (PICM)
}
Else {
Return (APIC)
}
}
Device (SBC3)
{
/* acpi smbus it should be 0x00040003 if 8131 present */
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
}
OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
Field (PIRQ, ByteAcc, Lock, Preserve)
{
PIBA, 8,
PIDC, 8
}
/*
OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
Field (TS3_, DWordAcc, NoLock, Preserve)
{
PTS3, 16
}
*/
}
Device (HPET)
{
Name (HPT, 0x00)
Name (_HID, EisaId ("PNP0103"))
Name (_UID, 0x00)
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
})
Return (BUF0)
}
}
Include ("amd8111_pic.asl")
Include ("amd8111_isa.asl")
Device (TP2P)
{
/* 8111 P2P and it should 0x00030000 when 8131 present*/
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
}
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
Else { Return (Package (0x02) { 0x08, 0x01 }) }
}
Device (USB0)
{
Name (_ADR, 0x00000000)
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
Else { Return (Package (0x02) { 0x0F, 0x01 }) }
}
}
Device (USB1)
{
Name (_ADR, 0x00000001)
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
Else { Return (Package (0x02) { 0x0F, 0x01 }) }
}
}
Name (APIC, Package (0x0C)
{
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
})
Name (PICM, Package (0x0C)
{
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //USB
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 },
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //Slot 4
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 },
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 }, //Slot 3
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}

176
src/mainboard/agami/aruma/dx/amd8111_isa.asl
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@ -1,176 +0,0 @@
/*
* Copyright 2005 AMD
*/
//AMD8111 isa
Device (ISA)
{
/* lpc 0x00040000 */
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
}
OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
Field (PIRY, ByteAcc, NoLock, Preserve)
{
Z000, 2, // Parallel Port Range
, 1,
ECP, 1, // ECP Enable
FDC1, 1, // Floppy Drive Controller 1
FDC2, 1, // Floppy Drive Controller 2
Offset (0x01),
Z001, 3, // Serial Port A Range
SAEN, 1, // Serial Post A Enabled
Z002, 3, // Serial Port B Range
SBEN, 1 // Serial Post B Enabled
}
Device (PIC)
{
Name (_HID, EisaId ("PNP0000"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
IRQ (Edge, ActiveHigh, Exclusive) {2}
})
}
Device (DMA1)
{
Name (_HID, EisaId ("PNP0200"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
DMA (Compatibility, NotBusMaster, Transfer16) {4}
})
}
Device (TMR)
{
Name (_HID, EisaId ("PNP0100"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
IRQ (Edge, ActiveHigh, Exclusive) {0}
})
}
Device (RTC)
{
Name (_HID, EisaId ("PNP0B00"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
IRQ (Edge, ActiveHigh, Exclusive) {8}
})
}
Device (SPKR)
{
Name (_HID, EisaId ("PNP0800"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
})
}
Device (COPR)
{
Name (_HID, EisaId ("PNP0C04"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
IRQ (Edge, ActiveHigh, Exclusive) {13}
})
}
Device (SYSR)
{
Name (_HID, EisaId ("PNP0C02"))
Name (_UID, 0x00)
Name (SYR1, ResourceTemplate ()
{
IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
})
Method (_CRS, 0, NotSerialized)
{
Return (SYR1)
}
}
Device (MEM)
{
Name (_HID, EisaId ("PNP0C02"))
Name (_UID, 0x01)
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
})
// Read the Video Memory length
CreateDWordField (BUF0, 0x14, CLEN)
CreateDWordField (BUF0, 0x10, CBAS)
ShiftLeft (VGA1, 0x09, Local0)
Store (Local0, CLEN)
Return (BUF0)
}
}
Device (PS2M)
{
Name (_HID, EisaId ("PNP0F13"))
Name (_CRS, ResourceTemplate ()
{
IRQNoFlags () {12}
})
Method (_STA, 0, NotSerialized)
{
And (FLG0, 0x04, Local0)
If (LEqual (Local0, 0x04)) { Return (0x0F) }
Else { Return (0x00) }
}
}
Device (PS2K)
{
Name (_HID, EisaId ("PNP0303"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
IRQNoFlags () {1}
})
}
Include ("superio.asl")
}

360
src/mainboard/agami/aruma/dx/amd8111_pic.asl
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@ -1,360 +0,0 @@
/*
* Copyright 2005 AMD
*/
//AMD8111 pic LNKA B C D
Device (LNKA)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized)
{
And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
Else { Return (0x0B) } //Enabled
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFA, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFA)
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local1)
}
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFA, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFA, 0x01, IRA1)
CreateByteField (BUFA, 0x02, IRA2)
Store (0x00, Local3)
Store (0x00, Local4)
And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1)
If (LNot (LEqual (Local1, 0x00)))
{ // Routing enable
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRA1)
Store (Local4, IRA2)
}
Return (BUFA)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRA1)
CreateByteField (Arg0, 0x02, IRA2)
ShiftLeft (IRA2, 0x08, Local0)
Or (Local0, IRA1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA)
Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA)
}
}
Device (LNKB)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized)
{
And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) }
Else { Return (0x0B) }
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFB, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFB)
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local1)
}
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFB, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFB, 0x01, IRB1)
CreateByteField (BUFB, 0x02, IRB2)
Store (0x00, Local3)
Store (0x00, Local4)
And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
If (LNot (LEqual (Local1, 0x00)))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRB1)
Store (Local4, IRB2)
}
Return (BUFB)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRB1)
CreateByteField (Arg0, 0x02, IRB2)
ShiftLeft (IRB2, 0x08, Local0)
Or (Local0, IRB1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA)
ShiftLeft (Local1, 0x04, Local1)
Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA)
}
}
Device (LNKC)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x03)
Method (_STA, 0, NotSerialized)
{
And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) }
Else { Return (0x0B) }
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFA, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFA)
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local1)
}
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFA, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFA, 0x01, IRA1)
CreateByteField (BUFA, 0x02, IRA2)
Store (0x00, Local3)
Store (0x00, Local4)
And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1)
If (LNot (LEqual (Local1, 0x00)))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRA1)
Store (Local4, IRA2)
}
Return (BUFA)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRA1)
CreateByteField (Arg0, 0x02, IRA2)
ShiftLeft (IRA2, 0x08, Local0)
Or (Local0, IRA1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC)
Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC)
}
}
Device (LNKD)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x04)
Method (_STA, 0, NotSerialized)
{
And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) }
Else { Return (0x0B) }
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFB, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFB)
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local1)
}
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFB, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFB, 0x01, IRB1)
CreateByteField (BUFB, 0x02, IRB2)
Store (0x00, Local3)
Store (0x00, Local4)
And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
If (LNot (LEqual (Local1, 0x00)))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRB1)
Store (Local4, IRB2)
}
Return (BUFB)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRB1)
CreateByteField (Arg0, 0x02, IRB2)
ShiftLeft (IRB2, 0x08, Local0)
Or (Local0, IRB1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC)
ShiftLeft (Local1, 0x04, Local1)
Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC)
}
}

119
src/mainboard/agami/aruma/dx/amd8131.asl
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@ -1,119 +0,0 @@
/*
* Copyright 2005 AMD
*/
Device (PG0A)
{
/* 8132 pcix bridge*/
Method (_ADR, 0, NotSerialized)
{
Return (DADD(GHCD(HCIN, 0), 0x00000000))
}
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
Else { Return (Package (0x02) { 0x29, 0x01 }) }
}
Name (APIC, Package (0x14)
{
// Slot A - PIRQ BCDA
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
//Cypress Slot A - PIRQ BCDA
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
//Cypress Slot B - PIRQ CDAB
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
//Cypress Slot C - PIRQ DABC
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
//Cypress Slot D - PIRQ ABCD
Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
})
Name (PICM, Package (0x14)
{
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },//Slot 2
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 },
Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 },
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKD, 0x00 },
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKA, 0x00 },
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKD, 0x00 },
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKA, 0x00 },
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },
Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}
Device (PG0B)
{
/* 8132 pcix bridge*/
Method (_ADR, 0, NotSerialized)
{
Return (DADD(GHCD(HCIN, 0), 0x00010000))
}
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
Else { Return (Package (0x02) { 0x22, 0x01 }) }
}
Name (APIC, Package (0x04)
{
// Slot A - PIRQ ABCD
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
})
Name (PICM, Package (0x04)
{
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },//Slot 1
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}

119
src/mainboard/agami/aruma/dx/amd8131_1.asl
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@ -1,119 +0,0 @@
/*
* Copyright 2005 AMD
*/
Device (PG1A)
{
/* 8132 pcix bridge*/
Method (_ADR, 0, NotSerialized)
{
Return (DADD(GHCD(HCIN, 1), 0x00000000))
}
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
Else { Return (Package (0x02) { 0x29, 0x01 }) }
}
Name (APIC, Package (0x14)
{
// Slot A - PIRQ BCDA
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
//Cypress Slot A - PIRQ BCDA
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
//Cypress Slot B - PIRQ CDAB
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
//Cypress Slot C - PIRQ DABC
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
//Cypress Slot D - PIRQ ABCD
Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
})
Name (PICM, Package (0x14)
{
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },//Slot 2
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 },
Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 },
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKD, 0x00 },
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKA, 0x00 },
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKD, 0x00 },
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKA, 0x00 },
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },
Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}
Device (PG1B)
{
/* 8132 pcix bridge*/
Method (_ADR, 0, NotSerialized)
{
Return (DADD(GHCD(HCIN, 1), 0x00010000))
}
Method (_PRW, 0, NotSerialized)
{
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
Else { Return (Package (0x02) { 0x22, 0x01 }) }
}
Name (APIC, Package (0x04)
{
// Slot A - PIRQ ABCD
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
})
Name (PICM, Package (0x04)
{
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },//Slot 1
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}

315
src/mainboard/agami/aruma/dx/amdk8_util.asl
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@ -1,315 +0,0 @@
/*
* Copyright 2005 AMD
*/
//AMD k8 util for BUSB and res range
Scope (\_SB)
{
Name (OSTB, Ones)
Method (OSTP, 0, NotSerialized)
{
If (LEqual (^OSTB, Ones))
{
Store (0x00, ^OSTB)
}
Return (^OSTB)
}
Method (SEQL, 2, Serialized)
{
Store (SizeOf (Arg0), Local0)
Store (SizeOf (Arg1), Local1)
If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
Name (BUF0, Buffer (Local0) {})
Store (Arg0, BUF0)
Name (BUF1, Buffer (Local0) {})
Store (Arg1, BUF1)
Store (Zero, Local2)
While (LLess (Local2, Local0))
{
Store (DerefOf (Index (BUF0, Local2)), Local3)
Store (DerefOf (Index (BUF1, Local2)), Local4)
If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
Increment (Local2)
}
Return (One)
}
Method (DADD, 2, NotSerialized)
{
Store( Arg1, Local0)
Store( Arg0, Local1)
Add( ShiftLeft(Local1,16), Local0, Local0)
Return (Local0)
}
Method (GHCE, 1, NotSerialized) // check if the HC enabled
{
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
Else { Return (0x00) }
}
Method (GHCN, 1, NotSerialized) // get the node num for the HC
{
Store (0x00, Local0)
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
Return (Local0)
}
Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
{
Store (0x00, Local0)
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
Return (Local0)
}
Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
{
Store (0x00, Local0)
Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
Return (Local0)
}
Method (GBUS, 2, NotSerialized)
{
Store (0x00, Local0)
While (LLess (Local0, 0x04))
{
Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
If (LEqual (And (Local1, 0x03), 0x03))
{
If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
{
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
{
Return (ShiftRight (And (Local1, 0x00FF0000), 0x10))
}
}
}
Increment (Local0)
}
Return (0x00)
}
Method (GWBN, 2, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Address Space Granularity
0x0000, // Address Range Minimum
0x0000, // Address Range Maximum
0x0000, // Address Translation Offset
0x0000,,,)
})
CreateWordField (BUF0, 0x08, BMIN)
CreateWordField (BUF0, 0x0A, BMAX)
CreateWordField (BUF0, 0x0E, BLEN)
Store (0x00, Local0)
While (LLess (Local0, 0x04))
{
Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
If (LEqual (And (Local1, 0x03), 0x03))
{
If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
{
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
{
Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN)
Store (ShiftRight (Local1, 0x18), BMAX)
Subtract (BMAX, BMIN, BLEN)
Increment (BLEN)
Return (RTAG (BUF0))
}
}
}
Increment (Local0)
}
Return (RTAG (BUF0))
}
Method (GMEM, 2, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Address Space Granularity
0x00000000, // Address Range Minimum
0x00000000, // Address Range Maximum
0x00000000, // Address Translation Offset
0x00000000,,,
, AddressRangeMemory, TypeStatic)
})
CreateDWordField (BUF0, 0x0A, MMIN)
CreateDWordField (BUF0, 0x0E, MMAX)
CreateDWordField (BUF0, 0x16, MLEN)
Store (0x00, Local0)
Store (0x00, Local4)
Store (0x00, Local3)
While (LLess (Local0, 0x10))
{
Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
Increment (Local0)
Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
If (LEqual (And (Local1, 0x03), 0x03))
{
If (LEqual (Arg0, And (Local2, 0x07)))
{
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
{
Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
Or (MMAX, 0xFFFF, MMAX)
Subtract (MMAX, MMIN, MLEN)
If (Local4)
{
Concatenate (RTAG (BUF0), Local3, Local5)
Store (Local5, Local3)
}
Else
{
If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
{
Store (\_SB.PCI0.TOM1, MMIN)
Subtract (MMAX, MMIN, MLEN)
Increment (MLEN)
}
Store (RTAG (BUF0), Local3)
}
Increment (Local4)
}
}
}
Increment (Local0)
}
If (LNot (Local4))
{
Store (BUF0, Local3)
}
Return (Local3)
}
Method (GIOR, 2, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x00000000, // Address Space Granularity
0x00000000, // Address Range Minimum
0x00000000, // Address Range Maximum
0x00000000, // Address Translation Offset
0x00000000,,,
, TypeStatic)
})
CreateDWordField (BUF0, 0x0A, PMIN)
CreateDWordField (BUF0, 0x0E, PMAX)
CreateDWordField (BUF0, 0x16, PLEN)
Store (0x00, Local0)
Store (0x00, Local4)
Store (0x00, Local3)
While (LLess (Local0, 0x08))
{
Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
Increment (Local0)
Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
If (LEqual (And (Local1, 0x03), 0x03))
{
If (LEqual (Arg0, And (Local2, 0x07)))
{
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
{
Store (And (Local1, 0x01FFF000), PMIN)
Store (And (Local2, 0x01FFF000), PMAX)
Or (PMAX, 0x0FFF, PMAX)
Subtract (PMAX, PMIN, PLEN)
Increment (PLEN)
If (Local4)
{
Concatenate (RTAG (BUF0), Local3, Local5)
Store (Local5, Local3)
}
Else
{
If (LGreater (PMAX, PMIN))
{
If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
{
Store (0x0D00, PMIN)
Subtract (PMAX, PMIN, PLEN)
Increment (PLEN)
}
Store (RTAG (BUF0), Local3)
Increment (Local4)
}
If (And (Local1, 0x10))
{
Store (0x03B0, PMIN)
Store (0x03DF, PMAX)
Store (0x30, PLEN)
If (Local4)
{
Concatenate (RTAG (BUF0), Local3, Local5)
Store (Local5, Local3)
}
Else
{
Store (RTAG (BUF0), Local3)
}
}
}
Increment (Local4)
}
}
}
Increment (Local0)
}
If (LNot (Local4))
{
Store (RTAG (BUF0), Local3)
}
Return (Local3)
}
Method (RTAG, 1, NotSerialized)
{
Store (Arg0, Local0)
Store (SizeOf (Local0), Local1)
Subtract (Local1, 0x02, Local1)
Multiply (Local1, 0x08, Local1)
CreateField (Local0, 0x00, Local1, RETB)
Store (RETB, Local2)
Return (Local2)
}
}

235
src/mainboard/agami/aruma/dx/dsdt_lb.dsl
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@ -1,235 +0,0 @@
/*
* Copyright 2005 AMD
*/
DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
{
Scope (_PR)
{
Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
Processor (CPU1, 0x01, 0x00000000, 0x00) {}
Processor (CPU2, 0x02, 0x00000000, 0x00) {}
Processor (CPU3, 0x03, 0x00000000, 0x00) {}
}
Method (FWSO, 0, NotSerialized) { }
Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
Scope (_SB)
{
Device (PCI0)
{
/* BUS0 root bus */
/*
//hardcode begin
Name (BUSN, Package (0x04) { 0x04010003, 0x06050013, 0x00000000, 0x00000000 })
Name (MMIO, Package (0x10) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00f43003, 0x00f44f01, 0x0000d003, 0x00efff01, 0x00f40003, 0x00f42f00, 0x00f45003, 0x00f44f00 })
Name (PCIO, Package (0x08) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00001003, 0x00001000, 0x00002003, 0x00002001 })
Name (SBLK, 0x00)
Name (TOM1, 0x40000000)
// for AMD opteron we could have four chains, so we will have PCI1, PCI2, PCI3, PCI4
// PCI1 must be SBLK Chain
// If you have HT IO card that is connected to PCI2, PCI3, PCI4, then you man put Device in SSDT2, SSDT3, SSDT4,
// in acpi_tables.c you can link those SSDT to RSDT according to it's presence.
// Otherwise put the PCI2, PCI3, PCI4 in this dsdt
Name (HCLK, Package (0x04) { 0x00000001, 0x00000011, 0x00000000, 0x00000000 }) //[0,3]=1 enable [4,7]=node_id, [8,15]=linkn
Name (SBDN, 3) // 8111 UnitID Base
//hardcode end
*/
External (BUSN)
External (MMIO)
External (PCIO)
External (SBLK)
External (TOM1)
External (HCLK)
External (SBDN)
External (HCDN)
Name (_HID, EisaId ("PNP0A03"))
Name (_ADR, 0x00180000)
Name (_UID, 0x01)
Name (_BBN, 0)
// define L1IC Link1 on node0 init completed, so node1 is installed
// We must make sure our bus is 0 ?
OperationRegion (LDT1, PCI_Config, 0xA4, 0x01)
Field (LDT1, ByteAcc, Lock, Preserve)
{
, 5,
L1IC, 1
}
}
Device (PCI1)
{
Name (HCIN, 0x00) // HC1
// BUS 1 first HT Chain
Name (_HID, EisaId ("PNP0A03"))
Name (_ADR, 0x00180000) // Fake
Name (_UID, 0x02)
Method (_BBN, 0, NotSerialized)
{
Return (GBUS (0x00, \_SB.PCI0.SBLK))
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, // Address Space Granularity
0x8100, // Address Range Minimum
0xFFFF, // Address Range Maximum
0x0000, // Address Translation Offset
0x7F00,,,
, TypeStatic) //8100h-FFFFh
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Address Space Granularity
0x000C0000, // Address Range Minimum
0x00000000, // Address Range Maximum
0x00000000, // Address Translation Offset
0x00000000,,,
, AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, // Address Space Granularity
0x0000, // Address Range Minimum
0x03AF, // Address Range Maximum
0x0000, // Address Translation Offset
0x03B0,,,
, TypeStatic) //0-CF7h
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, // Address Space Granularity
0x03E0, // Address Range Minimum
0x0CF7, // Address Range Maximum
0x0000, // Address Translation Offset
0x0918,,,
, TypeStatic) //0-CF7h
})
\_SB.OSTP ()
CreateDWordField (BUF0, 0x3E, VLEN)
CreateDWordField (BUF0, 0x36, VMAX)
CreateDWordField (BUF0, 0x32, VMIN)
ShiftLeft (VGA1, 0x09, Local0)
Add (VMIN, Local0, VMAX)
Decrement (VMAX)
Store (Local0, VLEN)
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
Return (Local3)
}
Include ("pci1_hc.asl")
}
}
Scope (_GPE)
{
Method (_L08, 0, NotSerialized)
{
Notify (\_SB.PCI1, 0x02) //PME# Wakeup
}
Method (_L0F, 0, NotSerialized)
{
Notify (\_SB.PCI1.TP2P.USB0, 0x02) //USB Wakeup
}
Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
{
Notify (\_SB.PCI1.PG0B, 0x02)
}
Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
{
Notify (\_SB.PCI1.PG0A, 0x02)
}
}
Method (_PTS, 1, NotSerialized)
{
Or (Arg0, 0xF0, Local0)
Store (Local0, DBG1)
}
/*
Method (_WAK, 1, NotSerialized)
{
Or (Arg0, 0xE0, Local0)
Store (Local0, DBG1)
}
*/
Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
{
Store (Arg0, PICF)
}
OperationRegion (DEBG, SystemIO, 0x80, 0x01)
Field (DEBG, ByteAcc, Lock, Preserve)
{
DBG1, 8
}
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
Field (EXTM, WordAcc, Lock, Preserve)
{
AMEM, 32
}
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
Field (VGAM, ByteAcc, Lock, Preserve)
{
VGA1, 8
}
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
Field (GRAM, ByteAcc, Lock, Preserve)
{
Offset (0x10),
FLG0, 8
}
OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
Field (GSTS, ByteAcc, NoLock, Preserve)
{
, 4,
IRQR, 1
}
OperationRegion (Z007, SystemIO, 0x21, 0x01)
Field (Z007, ByteAcc, NoLock, Preserve)
{
Z008, 8
}
OperationRegion (Z009, SystemIO, 0xA1, 0x01)
Field (Z009, ByteAcc, NoLock, Preserve)
{
Z00A, 8
}
Include ("amdk8_util.asl")
}

2
src/mainboard/agami/aruma/dx/pci1_hc.asl
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@ -1,2 +0,0 @@
Include ("amd8111.asl") //real SB at first
Include ("amd8131.asl")

69
src/mainboard/agami/aruma/dx/pci2.asl
View File

@ -1,69 +0,0 @@
/*
* Copyright 2005 AMD
*/
DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
{
Scope (_SB)
{
External (DADD, MethodObj)
External (GHCE, MethodObj)
External (GHCN, MethodObj)
External (GHCL, MethodObj)
External (GHCD, MethodObj)
External (GNUS, MethodObj)
External (GIOR, MethodObj)
External (GMEM, MethodObj)
External (GWBN, MethodObj)
External (GBUS, MethodObj)
External (PICF)
External (\_SB.PCI1.LNKA, DeviceObj)
External (\_SB.PCI1.LNKB, DeviceObj)
External (\_SB.PCI1.LNKC, DeviceObj)
External (\_SB.PCI1.LNKD, DeviceObj)
Device (PCI2)
{
// BUS ? Second HT Chain
Name (HCIN, 0x01) // HC2
Name (_HID, "PNP0A03")
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
{
Return (DADD(GHCN(HCIN), 0x00180000))
}
Name (_UID, 0x03)
Method (_BBN, 0, NotSerialized)
{
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
}
Method (_STA, 0, NotSerialized)
{
Return (\_SB.GHCE(HCIN))
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate () { })
Store( GHCN(HCIN), Local4)
Store( GHCL(HCIN), Local5)
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
Return (Local3)
}
Include ("pci2_hc.asl")
}
}
}

3
src/mainboard/agami/aruma/dx/pci2_hc.asl
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@ -1,3 +0,0 @@
Include ("amd8131.asl")
Include ("amd8131_1.asl")

69
src/mainboard/agami/aruma/dx/pci3.asl
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@ -1,69 +0,0 @@
/*
* Copyright 2005 AMD
*/
DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
{
Scope (_SB)
{
External (DADD, MethodObj)
External (GHCE, MethodObj)
External (GHCN, MethodObj)
External (GHCL, MethodObj)
External (GHCD, MethodObj)
External (GNUS, MethodObj)
External (GIOR, MethodObj)
External (GMEM, MethodObj)
External (GWBN, MethodObj)
External (GBUS, MethodObj)
External (PICF)
External (\_SB.PCI1.LNKA, DeviceObj)
External (\_SB.PCI1.LNKB, DeviceObj)
External (\_SB.PCI1.LNKC, DeviceObj)
External (\_SB.PCI1.LNKD, DeviceObj)
Device (PCI3)
{
// BUS ? Second HT Chain
Name (HCIN, 0x02) // HC3
Name (_HID, "PNP0A03")
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
{
Return (DADD(GHCN(HCIN), 0x00180000))
}
Name (_UID, 0x04)
Method (_BBN, 0, NotSerialized)
{
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
}
Method (_STA, 0, NotSerialized)
{
Return (\_SB.GHCE(HCIN))
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate () { })
Store( GHCN(HCIN), Local4)
Store( GHCL(HCIN), Local5)
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
Return (Local3)
}
Include ("pci2_hc.asl")
}
}
}

69
src/mainboard/agami/aruma/dx/pci4.asl
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@ -1,69 +0,0 @@
/*
* Copyright 2005 AMD
*/
DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
{
Scope (_SB)
{
External (DADD, MethodObj)
External (GHCE, MethodObj)
External (GHCN, MethodObj)
External (GHCL, MethodObj)
External (GHCD, MethodObj)
External (GNUS, MethodObj)
External (GIOR, MethodObj)
External (GMEM, MethodObj)
External (GWBN, MethodObj)
External (GBUS, MethodObj)
External (PICF)
External (\_SB.PCI1.LNKA, DeviceObj)
External (\_SB.PCI1.LNKB, DeviceObj)
External (\_SB.PCI1.LNKC, DeviceObj)
External (\_SB.PCI1.LNKD, DeviceObj)
Device (PCI4)
{
// BUS ? Second HT Chain
Name (HCIN, 0x03) // HC4
Name (_HID, "PNP0A03")
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
{
Return (DADD(GHCN(HCIN), 0x00180000))
}
Name (_UID, 0x05)
Method (_BBN, 0, NotSerialized)
{
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
}
Method (_STA, 0, NotSerialized)
{
Return (\_SB.GHCE(HCIN))
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate () { })
Store( GHCN(HCIN), Local4)
Store( GHCL(HCIN), Local5)
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
Return (Local3)
}
Include ("pci2_hc.asl")
}
}
}

1
src/mainboard/agami/aruma/dx/superio.asl
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@ -1 +0,0 @@
// Include ("w83627hf.asl")

151
src/mainboard/agami/aruma/fadt.c
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@ -1,151 +0,0 @@
/*
* ACPI - create the Fixed ACPI Description Tables (FADT)
* (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
*/
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
extern unsigned pm_base; /* pm_base should be set in sb acpi */
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
printk_debug("pm_base: 0x%04x\n", pm_base);
/* Prepare the header */
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = 244;
header->revision = 1;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, "COREBOOT", 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = 0;
fadt->firmware_ctrl = (u32) facs;
fadt->dsdt = (u32) dsdt;
// 3=Workstation,4=Enterprise Server, 7=Performance Server
fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9;
// disable system management mode by setting to 0:
fadt->smi_cmd = 0; //pm_base+0x2f;
fadt->acpi_enable = 0xf0;
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
fadt->pm1a_evt_blk = pm_base;
fadt->pm1b_evt_blk = 0x0000;
fadt->pm1a_cnt_blk = pm_base + 0x04;
fadt->pm1b_cnt_blk = 0x0000;
fadt->pm2_cnt_blk = 0x0000;
fadt->pm_tmr_blk = pm_base + 0x08;
fadt->gpe0_blk = pm_base + 0x20;
fadt->gpe1_blk = pm_base + 0xb0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 0;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 4;
fadt->gpe1_blk_len = 8;
fadt->gpe1_base = 16;
fadt->cst_cnt = 0xe3;
fadt->p_lvl2_lat = 101;
fadt->p_lvl3_lat = 1001;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0; // 0x7d these have to be
fadt->mon_alrm = 0; // 0x7e added to cmos.layout
fadt->century = 0; // 0x7f to make rtc alrm work
fadt->iapc_boot_arch = 0x3; // See table 5-11
fadt->flags = 0x25;
fadt->res2 = 0;
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 6;
fadt->x_firmware_ctl_l = (u32) facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32) dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = pm_base;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 4;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = pm_base + 4;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 2;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = 0x0;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = pm_base + 0x08;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = pm_base + 0x20;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 64;
fadt->x_gpe1_blk.bit_offset = 16;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = pm_base + 0xb0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum =
acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
}

66
src/mainboard/agami/aruma/failover.c
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@ -1,66 +0,0 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/reset_test.c"
static unsigned long main(unsigned long bist)
{
unsigned nodeid;
/* Make cerain my local apic is useable */
enable_lapic();
nodeid=lapicid();
/* Is this a cpu only reset? */
if (early_mtrr_init_detected()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

164
src/mainboard/agami/aruma/get_bus_conf.c
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@ -1,164 +0,0 @@
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/dualcore.h>
#endif
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
unsigned char bus_isa = 7;
unsigned char bus_8111_0 = 1;
unsigned char bus_8111_1 = 4;
unsigned char bus_8131[7][3]; // another 6 8131
unsigned apicid_8111;
unsigned apicid_8131[7][2];
unsigned sblk;
unsigned pci1234[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
0x0000f10,
0x0000f20,
0x0000f30,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0
};
unsigned hc_possible_num;
unsigned sbdn;
unsigned hcdn[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
0x20202020,
0x20202020,
0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
};
unsigned sbdnx[7]; // for all 8131
extern void get_sblk_pci1234(void);
static unsigned get_bus_conf_done = 0;
void get_bus_conf(void)
{
unsigned apicid_base;
device_t dev;
int i;
if (get_bus_conf_done == 1)
return; //do it only once
get_bus_conf_done = 1;
hc_possible_num = ARRAY_SIZE(pci1234);
get_sblk_pci1234();
sbdn = ((hcdn[0] >> 8) & 0xff); // first byte of first chain
sbdnx[0] = (hcdn[0] & 0xff);
for (i = 0; i < hc_possible_num; i++) {
sbdnx[i * 2 + 1] = hcdn[i] & 0xff;
sbdnx[i * 2 + 2] = (hcdn[i] >> 8) & 0xff;
}
bus_8131[0][0] = (pci1234[0] >> 16) & 0xff;
bus_8111_0 = bus_8131[0][0];
/* 8111 */
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn, 0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
// printk_debug("bus_isa=%d\n",bus_isa);
} else {
printk_debug
("ERROR - could not find PCI %02x:03.0, using defaults\n",
bus_8111_0);
}
/* 8131-1 */
bus_8131[0][0] = 1;
dev = dev_find_slot(bus_8131[0][0], PCI_DEVFN(sbdnx[1], 0));
if (dev) {
bus_8131[0][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk_debug
("ERROR - could not find PCI %02x:01.0, using defaults\n",
bus_8131[0][0]);
}
/* 8132-2 */
dev = dev_find_slot(bus_8131[0][0], PCI_DEVFN(sbdnx[1] + 1, 0));
if (dev) {
bus_8131[0][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
} else {
printk_debug
("ERROR - could not find PCI %02x:02.0, using defaults\n",
bus_8131[0][0]);
}
apicid_base = get_apicid_base(15);
apicid_8111 = apicid_base++;
apicid_8131[0][0] = apicid_base++;
apicid_8131[0][1] = apicid_base++;
/* HT chain 1 */
for (i = 1; i < 4; i++) {
if (pci1234[i] & 0x1) {
int j = (i - 1) * 2 + 1;
bus_8131[j][0] = (pci1234[i] >> 16) & 0xff;
/* 8131 */
dev = dev_find_slot(bus_8131[j][0], PCI_DEVFN(sbdnx[j], 0));
if (dev) {
bus_8131[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
apicid_8131[j][0] = apicid_base++;
dev = dev_find_slot(bus_8131[j][0], PCI_DEVFN(sbdnx[j] + 1, 0));
if (dev) {
bus_8131[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
apicid_8131[j][1] = apicid_base++;
bus_8131[j + 1][0] = bus_8131[j][0];
/* 8131 */
dev = dev_find_slot(bus_8131[j + 1][0], PCI_DEVFN(sbdnx[j + 1], 0));
if (dev) {
bus_8131[j + 1][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
apicid_8131[j + 1][0] = apicid_base++;
dev = dev_find_slot(bus_8131[i + 1][0], PCI_DEVFN(sbdnx[j + 1] + 1, 0));
if (dev) {
bus_8131[j + 1][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
apicid_8131[j + 1][0] = apicid_base++;
}
}
}

60
src/mainboard/agami/aruma/irq_tables.c
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@ -1,60 +0,0 @@
#include <arch/pirq_routing.h>
#include <device/pci.h>
#define IRQ_ROUTER_BUS 1
#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
#define IRQ_ROUTER_VENDOR 0x1022
#define IRQ_ROUTER_DEVICE 0x746b
#define AVAILABLE_IRQS 0xdef8
#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
{ bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
{linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
/* Each IRQ_SLOT entry consists of:
* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
*/
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */
IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
IRQ_ROUTER_VENDOR, /* Vendor */
IRQ_ROUTER_DEVICE, /* Device */
0x00, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x6a, /* u8 checksum , mod 256 checksum must give zero */
{ /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
IRQ_SLOT(0, 0x01,4,0, 1,2,3,4 ), /* 8111 PCI bridge */
IRQ_SLOT(0, 0x04,0,0, 4,0,0,0 ), /* 8111 USB */
IRQ_SLOT(1, 0x06,1,0, 2,3,4,1 ), /* ???? was: bus A*/
IRQ_SLOT(2, 0x07,1,0, 2,3,4,1 ), /* ???? was: bus 9*/
IRQ_SLOT(3, 0x0a,1,0, 2,3,4,1 ), /* IBM PCI-X <-> PCI-X */
IRQ_SLOT(4, 0x08,1,0, 2,3,4,1 ), /* IBM PCI-X <-> PCI-X */
IRQ_SLOT(0, 0x04,4,0, 1,0,0,0 ), /* ATI Rage */
IRQ_SLOT(0, 0x06,2,0, 3,4,0,0 ), /* ???? was: bus A */
IRQ_SLOT(0, 0x07,2,0, 3,4,0,0 ), /* ???? was: bus 9 */
IRQ_SLOT(0, 0x0a,2,0, 3,4,0,0 ), /* Intel 82546EB GBit */
IRQ_SLOT(0, 0x08,2,0, 3,4,0,0 ), /* Intel 82546EB GBit */
IRQ_SLOT(0, 0x0d,1,0, 1,0,0,0 ), /* Marvell MV88SX5080 SATA */
IRQ_SLOT(0, 0x0d,2,0, 2,0,0,0 ), /* Marvell MV88SX5080 SATA */
IRQ_SLOT(0, 0x0e,1,0, 1,2,3,4 ), /* Intel Memory Controller 031a */
IRQ_SLOT(0, 0x0f,1,0, 1,0,0,0 ), /* Marvell MV88SX5080 SATA */
IRQ_SLOT(0, 0x04,5,0, 2,0,0,0 ), /* Intel 8255 Ethernet */
IRQ_SLOT(5, 0x10,1,0, 1,2,3,4 ), /* ???? was: bus C */
IRQ_SLOT(0, 0x12,1,0, 1,0,0,0 ), /* Marvell MV88SX5080 SATA */
IRQ_SLOT(0, 0x12,2,0, 2,0,0,0 ), /* Marvell MV88SX5080 SATA */
IRQ_SLOT(0, 0x13,1,0, 1,2,3,4 ), /* Intel Memory Controller 031b */
IRQ_SLOT(0, 0x14,1,0, 1,0,0,0 ), /* Marvell MV88SX5080 SATA */
IRQ_SLOT(6, 0x15,1,0, 1,2,3,4 ), /* ???? was: bus 11 */
/* Let Linux know about bus 1 */
IRQ_SLOT(0, 1,4,3, 0,0,0,0 ),
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}

330
src/mainboard/agami/aruma/mainboard.c
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@ -1,330 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include <part/hard_reset.h>
#include <device/smbus.h>
#include <delay.h>
#include <arch/io.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include <cpu/amd/model_fxx_rev.h>
#include "chip.h"
#include "pc80/mc146818rtc.h"
#undef DEBUG
#define DEBUG 0
#if DEBUG
static void debug_init(device_t dev)
{
unsigned bus;
unsigned devfn;
#if 0
for(bus = 0; bus < 256; bus++) {
for(devfn = 0; devfn < 256; devfn++) {
int i;
dev = dev_find_slot(bus, devfn);
if (!dev) {
continue;
}
if (!dev->enabled) {
continue;
}
printk_info("%02x:%02x.%0x aka %s\n",
bus, devfn >> 3, devfn & 7, dev_path(dev));
for(i = 0; i < 256; i++) {
if ((i & 0x0f) == 0) {
printk_info("%02x:", i);
}
printk_info(" %02x", pci_read_config8(dev, i));
if ((i & 0x0f) == 0xf) {
printk_info("\n");
}
}
printk_info("\n");
}
}
#endif
#if 0
msr_t msr;
unsigned index;
unsigned eax, ebx, ecx, edx;
index = 0x80000007;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
index, eax, ebx, ecx, edx);
if (edx & (3 << 1)) {
index = 0xC0010042;
printk_debug("Reading msr: 0x%08x\n", index);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x\n",
index, msr.hi, msr.hi);
}
#endif
}
static void debug_noop(device_t dummy)
{
}
static struct device_operations debug_operations = {
.read_resources = debug_noop,
.set_resources = debug_noop,
.enable_resources = debug_noop,
.init = debug_init,
};
static unsigned int scan_root_bus(device_t root, unsigned int max)
{
struct device_path path;
device_t debug;
max = root_dev_scan_bus(root, max);
path.type = DEVICE_PATH_PNP;
path.u.pnp.port = 0;
path.u.pnp.device = 0;
debug = alloc_dev(&root->link[1], &path);
debug->ops = &debug_operations;
return max;
}
#endif
#if 1
static void handle_smbus_error(int value, const char *msg)
{
if (value >= 0) {
return;
}
switch(value) {
case SMBUS_WAIT_UNTIL_READY_TIMEOUT:
printk_emerg("SMBUS wait until ready timed out - resetting...");
hard_reset();
break;
case SMBUS_WAIT_UNTIL_DONE_TIMEOUT:
printk_emerg("SMBUS wait until done timed out - resetting...");
hard_reset();
break;
default:
die(msg);
break;
}
}
#define ADM1026_DEVICE 0x2d /* Either 0x2c, 0x2d or 0x2e. */
#define ADM1026_REG_CONFIG1 0x00
#define CFG1_MONITOR 0x01
#define CFG1_INT_ENABLE 0x02
#define CFG1_INT_CLEAR 0x04
#define CFG1_AIN8_9 0x08
#define CFG1_THERM_HOT 0x10
#define CFT1_DAC_AFC 0x20
#define CFG1_PWM_AFC 0x40
#define CFG1_RESET 0x80
#define ADM1026_REG_CONFIG2 0x01
#define ADM1026_REG_CONFIG3 0x07
#define BILLION 1000000000UL
static void verify_cpu_voltage(const char *name,
device_t dev, unsigned int reg,
unsigned factor, unsigned cpu_volts, unsigned delta)
{
unsigned nvolts_lo, nvolts_hi;
unsigned cpuvolts_hi, cpuvolts_lo;
int value;
int loops;
loops = 1000;
do {
value = smbus_read_byte(dev, reg);
handle_smbus_error(value, "SMBUS read byte failed");
} while ((--loops > 0) && value == 0);
/* Convert the byte value to nanoVolts.
* My accuracy is nowhere near that good but I don't
* have to round so the math is simple.
* I can only go up to about 4.2 Volts this way so my range is
* limited.
*/
nvolts_lo = ((unsigned)value * factor);
nvolts_hi = nvolts_lo + factor - 1;
/* Get the range of acceptable cpu voltage values */
cpuvolts_lo = cpu_volts - delta;
cpuvolts_hi = cpu_volts + delta;
if ((nvolts_lo < cpuvolts_lo) || (nvolts_hi > cpuvolts_hi)) {
printk_emerg("%s at (%u.%09u-%u.%09u)Volts expected %u.%09u+/-%u.%09uVolts\n",
name,
nvolts_lo/BILLION, nvolts_lo%BILLION,
nvolts_hi/BILLION, nvolts_hi%BILLION,
cpu_volts/BILLION, cpu_volts%BILLION,
delta/BILLION, delta%BILLION);
die("");
}
printk_info("%s at (%u.%09u-%u.%09u)Volts\n",
name,
nvolts_lo/BILLION, nvolts_lo%BILLION,
nvolts_hi/BILLION, nvolts_hi%BILLION);
}
static void adm1026_enable_monitoring(device_t dev)
{
int result;
result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
handle_smbus_error(result, "ADM1026: cannot read config1");
result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET);
result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result);
handle_smbus_error(result, "ADM1026: cannot write to config1");
result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
handle_smbus_error(result, "ADM1026: cannot reread config1");
if (!(result & CFG1_MONITOR)) {
die("ADM1026: monitoring would not enable");
}
}
static unsigned k8_cpu_volts(void)
{
unsigned volts = ~0;
if (is_cpu_c0()) {
volts = 1500000000;
}
if (is_cpu_b3()) {
volts = 1550000000;
}
return volts;
}
static void verify_cpu_voltages(device_t dev)
{
unsigned cpu_volts;
unsigned delta;
#if 0
delta = 50000000;
#else
delta = 75000000;
#endif
cpu_volts = k8_cpu_volts();
if (cpu_volts == ~0) {
printk_info("Required cpu voltage unknwon not checking\n");
return;
}
/* I need to read registers 0x37 == Ain7CPU1 core 0x2d == VcppCPU0 core */
/* CPU1 core
* The sensor has a range of 0-2.5V and reports in
* 256 distinct steps.
*/
verify_cpu_voltage("CPU1 Vcore", dev, 0x37, 9765625,
cpu_volts, delta);
/* CPU0 core
* The sensor has range of 0-3.0V and reports in
* 256 distinct steps.
*/
verify_cpu_voltage("CPU0 Vcore", dev, 0x2d, 11718750,
cpu_volts, delta);
}
#define SMBUS_MUX 0x71
static void do_verify_cpu_voltages(void)
{
device_t smbus_dev;
device_t mux, sensor;
struct device_path mux_path, sensor_path;
int result;
int mux_setting;
/* Find the smbus controller */
smbus_dev = dev_find_device(0x1022, 0x746b, 0);
if (!smbus_dev) {
die("SMBUS controller not found\n");
}
/* Find the smbus mux */
mux_path.type = DEVICE_PATH_I2C;
mux_path.u.i2c.device = SMBUS_MUX;
mux = find_dev_path(smbus_dev, &mux_path);
if (!mux) {
die("SMBUS mux not found\n");
}
/* Find the adm1026 sensor */
sensor_path.type = DEVICE_PATH_I2C;
sensor_path.u.i2c.device = ADM1026_DEVICE;
sensor = find_dev_path(mux, &sensor_path);
if (!sensor) {
die("ADM1026 not found\n");
}
/* Set the mux to see the temperature sensors */
mux_setting = 1;
result = smbus_send_byte(mux, mux_setting);
handle_smbus_error(result, "SMBUS send byte failed\n");
result = smbus_recv_byte(mux);
handle_smbus_error(result, "SMBUS recv byte failed\n");
if (result != mux_setting) {
printk_emerg("SMBUS mux would not set to %d\n", mux_setting);
die("");
}
adm1026_enable_monitoring(sensor);
/* It takes 11.38ms to read a new voltage sensor value */
mdelay(12);
/* Read the cpu voltages and make certain everything looks sane */
verify_cpu_voltages(sensor);
}
#else
#define do_verify_cpu_voltages() do {} while(0)
#endif
static void fixup_aruma(void)
{
msr_t msr;
/* bit 6 (0x40) in MSR 0xC0010015
* disables the TLB cache flush filter
*/
msr=rdmsr(0xC0010015);
msr.lo |= 0x40;
wrmsr(0xC0010015, msr);
}
static void mainboard_init(device_t dev)
{
root_dev_init(dev);
printk_info("Initializing mainboard components... ");
// do_verify_cpu_voltages();
printk_info("ok\n");
printk_info("Initializing mainboard specific functions... ");
fixup_aruma();
printk_info("ok\n");
}
static void enable_dev(struct device *dev)
{
dev->ops->init = mainboard_init;
}
struct chip_operations mainboard_agami_aruma_ops = {
CHIP_NAME("AGAMI Aruma Mainboard")
.enable_dev = enable_dev,
};

246
src/mainboard/agami/aruma/mptable.c
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@ -1,246 +0,0 @@
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <cpu/x86/lapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#define WRITE_IOAPIC(bus,device,fn,id,version) \
do { \
device_t dev; \
struct resource *res; \
dev = dev_find_slot(bus, PCI_DEVFN(device,fn)); \
if (!dev) break; \
res = find_resource(dev, PCI_BASE_ADDRESS_0); \
if (!res) break; \
smp_write_ioapic(mc, id, version, res->base); \
} while(0);
unsigned get_apicid_base(unsigned ioapic_num);
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "AGAMI ";
static const char productid[12] = "ARUMA ";
struct mp_config_table *mc;
int i;
unsigned apicid_base;
unsigned char bus_isa;
device_t dev;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
/* Write busses */
bus_isa=22; // ISA
for (i=0; i<bus_isa; i++)
smp_write_bus(mc, i, "PCI ");
smp_write_bus(mc, bus_isa, "ISA ");
/* enable ext_apic_id */
#if 1
apicid_base = 1;
#else
apicid_base = get_apicid_base(15);
if(lapicid()>=0x10) {
apicid_base = 0;
}
#endif
printk_info("APIC ID BASE=0x%x\n",apicid_base);
/* I/O APICs */
smp_write_ioapic(mc, apicid_base, 0x11, 0xfec00000); // 8111 IOAPIC
/* Write all 8131 IOAPICs */
/* (8131: bus, dev, fn) , id, version */
WRITE_IOAPIC(0x01,1,1, apicid_base+1, 0x11);
WRITE_IOAPIC(0x01,2,1, apicid_base+2, 0x11);
WRITE_IOAPIC(0x05,1,1, apicid_base+3, 0x11);
WRITE_IOAPIC(0x05,2,1, apicid_base+4, 0x11);
WRITE_IOAPIC(0x05,3,1, apicid_base+5, 0x11);
WRITE_IOAPIC(0x05,4,1, apicid_base+6, 0x11);
WRITE_IOAPIC(0x0c,1,1, apicid_base+7, 0x11);
WRITE_IOAPIC(0x0c,2,1, apicid_base+8, 0x11);
WRITE_IOAPIC(0x0c,3,1, apicid_base+9, 0x11);
WRITE_IOAPIC(0x0c,4,1, apicid_base+10, 0x11);
WRITE_IOAPIC(0x11,1,1, apicid_base+11, 0x11);
WRITE_IOAPIC(0x11,2,1, apicid_base+12, 0x11);
WRITE_IOAPIC(0x11,3,1, apicid_base+13, 0x11);
WRITE_IOAPIC(0x11,4,1, apicid_base+14, 0x11);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_base, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_base, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_base, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_base, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_base, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_base, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_base, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_base, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_base, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_base, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_base, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_base, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, apicid_base, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1f, apicid_base, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x03, apicid_base, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x10, apicid_base, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x14, apicid_base, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x10, 0x5, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x11, 0x5, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x14, 0x5, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x15, 0x5, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x18, 0x5, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xb, 0x19, 0x5, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xa, 0x8, 0x5, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xa, 0x9, 0x5, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x10, 0x6, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x11, 0x6, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x14, 0x6, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x15, 0x6, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x18, 0x6, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, 0x19, 0x6, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, 0x8, 0x6, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, 0x9, 0x6, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xd, 0x4, 0x7, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xd, 0x8, 0x7, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xe, 0x4, 0x8, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0xf, 0x4, 0x9, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x12, 0x4, 0xb, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x12, 0x8, 0xb, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x13, 0x4, 0xc, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x14, 0x4, 0xd, 0x0);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/*
MP Config Extended Table Entries:
--
System Address Space
bus ID: 0 address type: I/O address
address base: 0x9000
address range: 0x2000
--
System Address Space
bus ID: 0 address type: I/O address
address base: 0x0
address range: 0x100
--
System Address Space
bus ID: 0 address type: memory address
address base: 0xa0000
address range: 0x20000
--
System Address Space
bus ID: 0 address type: memory address
address base: 0xaed00000
address range: 0x2200000
--
System Address Space
bus ID: 0 address type: prefetch address
address base: 0xb0f00000
address range: 0x100000
--
System Address Space
bus ID: 4 address type: I/O address
address base: 0xb000
address range: 0x2000
--
System Address Space
bus ID: 4 address type: memory address
address base: 0xb1000000
address range: 0x700000
--
System Address Space
bus ID: 4 address type: prefetch address
address base: 0xb1700000
address range: 0x500000
--
System Address Space
bus ID: 11 address type: memory address
address base: 0xb1c00000
address range: 0x400000
--
System Address Space
bus ID: 11 address type: prefetch address
address base: 0xb2000000
address range: 0x2400000
--
System Address Space
bus ID: 16 address type: memory address
address base: 0xb4400000
address range: 0x400000
--
System Address Space
bus ID: 16 address type: prefetch address
address base: 0xb4800000
address range: 0x4a400000
--
Bus Heirarchy
bus ID: 21 bus info: 0x01 parent bus ID: 0--
Compatibility Bus Address
bus ID: 0 address modifier: add
predefined range: 0x00000000--
Compatibility Bus Address
bus ID: 4 address modifier: subtract
predefined range: 0x00000000--
Compatibility Bus Address
bus ID: 11 address modifier: subtract
predefined range: 0x00000000--
Compatibility Bus Address
bus ID: 16 address modifier: subtract
predefined range: 0x00000000--
Compatibility Bus Address
bus ID: 0 address modifier: add
predefined range: 0x00000001--
Compatibility Bus Address
bus ID: 4 address modifier: subtract
predefined range: 0x00000001--
Compatibility Bus Address
bus ID: 11 address modifier: subtract
predefined range: 0x00000001--
Compatibility Bus Address
bus ID: 16 address modifier: subtract
predefined range: 0x00000001
*/
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v);
}

271
src/mainboard/agami/aruma/resourcemap.c
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@ -1,271 +0,0 @@
/*
* Agami Aruma needs a different resource map
*
*/
static void setup_aruma_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
/* DRAM Limit i Registers
* F1:0x44 i = 0
* F1:0x4C i = 1
* F1:0x54 i = 2
* F1:0x5C i = 3
* F1:0x64 i = 4
* F1:0x6C i = 5
* F1:0x74 i = 6
* F1:0x7C i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 3] Reserved
* [10: 8] Interleave select
* specifies the values of A[14:12] to use with interleave enable.
* [15:11] Reserved
* [31:16] DRAM Limit Address i Bits 39-24
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers
* F1:0x40 i = 0
* F1:0x48 i = 1
* F1:0x50 i = 2
* F1:0x58 i = 3
* F1:0x60 i = 4
* F1:0x68 i = 5
* F1:0x70 i = 6
* F1:0x78 i = 7
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 7: 2] Reserved
* [10: 8] Interleave Enable
* 000 = No interleave
* 001 = Interleave on A[12] (2 nodes)
* 010 = reserved
* 011 = Interleave on A[12] and A[14] (4 nodes)
* 100 = reserved
* 101 = reserved
* 110 = reserved
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
* [15:11] Reserved
* [13:16] DRAM Base Address i Bits 39-24
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0
* F1:0x8C i = 1
* F1:0x94 i = 2
* F1:0x9C i = 3
* F1:0xA4 i = 4
* F1:0xAC i = 5
* F1:0xB4 i = 6
* F1:0xBC i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = Reserved
* [ 6: 6] Reserved
* [ 7: 7] Non-Posted
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff10, // Link 1 CPU 0
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
* F1:0x88 i = 1
* F1:0x90 i = 2
* F1:0x98 i = 3
* F1:0xA0 i = 4
* F1:0xA8 i = 5
* F1:0xB0 i = 6
* F1:0xB8 i = 7
* [ 0: 0] Read Enable
* 0 = Reads disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes disabled
* 1 = Writes Enabled
* [ 2: 2] Cpu Disable
* 0 = Cpu can use this I/O range
* 1 = Cpu requests do not use this I/O range
* [ 3: 3] Lock
* 0 = base/limit registers i are read/write
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
* F1:0xCC i = 1
* F1:0xD4 i = 2
* F1:0xDC i = 3
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = reserved
* [11: 6] Reserved
* [24:12] PCI I/O Limit Address i
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff010, // CPU0 LDT1
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
* F1:0xC8 i = 1
* F1:0xD0 i = 2
* F1:0xD8 i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
* 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers
* F1:0xE0 i = 0
* F1:0xE4 i = 1
* F1:0xE8 i = 2
* F1:0xEC i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 2: 2] Device Number Compare Enable
* 0 = The ranges are based on bus number
* 1 = The ranges are ranges of devices on bus 0
* [ 3: 3] Reserved
* [ 6: 4] Destination Node
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 7] Reserved
* [ 9: 8] Destination Link
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 - Reserved
* [15:10] Reserved
* [23:16] Bus Number Base i
* This field defines the lowest bus number in configuration region i
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04000103, // CPU0 LDT1
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x0b050213, // CPU1 LDT2
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x100c0223, // CPU2 LDT2
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x15110133, // CPU3 LTD1
/* setup power management registers */
PCI_ADDR(0, 0x18, 3, 0x80), 0x80808080, 0x23070000, // PM control low
PCI_ADDR(0, 0x18, 3, 0x84), 0x80808080, 0x00132113, // PM control high
PCI_ADDR(0, 0x18, 3, 0xD8), 0x8E000000, 0x20002710, // Clock PM high
};
int max;
max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}

77
src/mainboard/agami/aruma/ssdt_lb_x.dsl
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@ -1,77 +0,0 @@
/*
* Copyright 2005 AMD
*/
DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-K8", "AMD-ACPI", 100925440)
{
/*
* These objects were referenced but not defined in this table
*/
External (\_SB_.PCI0, DeviceObj)
Scope (\_SB.PCI0)
{
Name (BUSN, Package (0x04)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444
})
Name (MMIO, Package (0x10)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee,
0x11111111,
0x22222222
})
Name (PCIO, Package (0x08)
{
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee
})
Name (SBLK, 0x11)
Name (TOM1, 0xaaaaaaaa)
Name (SBDN, 0xbbbbbbbb)
Name (HCLK, Package (0x08)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888
})
Name (HCDN, Package (0x08)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888
})
}
}

26
targets/agami/aruma/Config-abuild.lb
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@ -1,26 +0,0 @@
# This will make a target directory of ./VENDOR_MAINBOARD
target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
option DEFAULT_CONSOLE_LOGLEVEL=7
option MAXIMUM_CONSOLE_LOGLEVEL=7
option ROM_SIZE = (1024*1024)
option FALLBACK_SIZE = (1024*1024)
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x16100
option XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "fallback"

29
targets/agami/aruma/Config.lb
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# This will make a target directory of ./agami_aruma
target agami_aruma
mainboard agami/aruma
option DEFAULT_CONSOLE_LOGLEVEL=8
option MAXIMUM_CONSOLE_LOGLEVEL=8
#option DEFAULT_CONSOLE_LOGLEVEL=7
#option MAXIMUM_CONSOLE_LOGLEVEL=7
romimage "normal"
option ROM_SIZE = 512*1024-36*1024
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x17000
option XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload ../../../../../../filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x17000
option XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload ../../../../../../filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

24
targets/agami/aruma/Config1M.lb
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# This will make a target directory of ./agami_aruma
target agami_aruma
mainboard agami/aruma
#option DEFAULT_CONSOLE_LOGLEVEL=8
#option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=7
option MAXIMUM_CONSOLE_LOGLEVEL=7
option ROM_SIZE = (1024*1024)
option FALLBACK_SIZE = (1024*1024)
option CONFIG_COMPRESSED_PAYLOAD_LZMA = 1
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x14000
option XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-big"
payload ../../../../../../linux.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"

12
targets/agami/aruma/build
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#!/bin/bash
#
# script to generate rom image with builtin vga option rom.
# call from freebios2/targets
#
rm -rf agami/aruma/agami_aruma
./buildtarget agami/aruma/
cd agami/aruma/agami_aruma
make
mv agami_aruma.rom agami_aruma_novga.rom
cat ~/atiragexl.rom agami_aruma_novga.rom > agami_aruma.rom
cd ../../..