soc/intel/quark: Add ESRAM display to FSP 1.1
Add ESRAM display to FSP 1.1 TEST=Build and run on Galileo Gen2 Change-Id: Ia47b0bdba65606a7f0695332d298fc1e910b0e2f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18804 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -177,7 +177,6 @@ config DCACHE_RAM_SIZE
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config DISPLAY_ESRAM_LAYOUT
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bool "Display ESRAM layout"
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default n
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depends on PLATFORM_USES_FSP2_0
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help
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Select this option to display coreboot's use of ESRAM.
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@ -105,6 +105,39 @@ void soc_memory_init_params(struct romstage_params *params,
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if (!rmu_file)
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die("Microcode file (rmu.bin) not found.");
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/* Display the ESRAM layout */
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if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) {
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printk(BIOS_SPEW, "\nESRAM Layout:\n\n");
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printk(BIOS_SPEW,
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"+-------------------+ 0x80080000 - ESRAM end\n");
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if (_car_relocatable_data_end != (void *)0x80080000) {
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printk(BIOS_SPEW, "| |\n");
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printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
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_car_relocatable_data_end);
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}
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printk(BIOS_SPEW, "| coreboot data |\n");
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printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
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_car_stack_end);
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printk(BIOS_SPEW, "| coreboot stack |\n");
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printk(BIOS_SPEW, "+-------------------+ 0x%p",
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_car_stack_start);
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if (IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) {
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printk(BIOS_SPEW, "\n");
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printk(BIOS_SPEW, "| vboot data |\n");
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printk(BIOS_SPEW, "+-------------------+ 0x%08x",
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CONFIG_DCACHE_RAM_BASE);
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}
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printk(BIOS_SPEW, " (CONFIG_DCACHE_RAM_BASE)\n");
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printk(BIOS_SPEW, "| FSP data |\n");
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printk(BIOS_SPEW, "+-------------------+\n");
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printk(BIOS_SPEW, "| FSP stack |\n");
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printk(BIOS_SPEW, "+-------------------+\n");
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printk(BIOS_SPEW, "| FSP binary |\n");
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printk(BIOS_SPEW,
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"+-------------------+ 0x80000000 - ESRAM start\n\n");
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}
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/* Update the UPD data for MemoryInit */
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upd->AddrMode = config->AddrMode;
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upd->ChanMask = config->ChanMask;
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