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ACPI: Refactor ChromeOS specific ACPI GNVS 

The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.

If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.

If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.

Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.

Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2020-12-19 16:19:44 +02:00
parent c4a6628a6f
commit 66c6413c69
19 changed files with 19 additions and 100 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/acpi/chromeos-gnvs.c
View File

@ -5,11 +5,9 @@
#include <smbios.h>
#include <vendorcode/google/chromeos/gnvs.h>
void gnvs_assign_chromeos(void)
void gnvs_assign_chromeos(void *gnvs_section)
{
chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs());
if (!gnvs_chromeos)
return;
chromeos_acpi_t *gnvs_chromeos = gnvs_section;
chromeos_init_chromeos_acpi(gnvs_chromeos);
@ -22,7 +20,7 @@ void gnvs_assign_chromeos(void)
void gnvs_set_ecfw_rw(void)
{
chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs());
chromeos_acpi_t *gnvs_chromeos = chromeos_get_chromeos_acpi();
if (!gnvs_chromeos)
return;
@ -31,7 +29,7 @@ void gnvs_set_ecfw_rw(void)
void smbios_type0_bios_version(uintptr_t address)
{
chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs());
chromeos_acpi_t *gnvs_chromeos = chromeos_get_chromeos_acpi();
if (!gnvs_chromeos)
return;

11
src/acpi/gnvs.c
View File

@ -6,6 +6,7 @@
#include <console/console.h>
#include <string.h>
#include <types.h>
#include <vendorcode/google/chromeos/gnvs.h>
static void *gnvs;
@ -53,6 +54,14 @@ void *gnvs_get_or_create(void)
if (!gnvs_size)
return NULL;
/* Match with OpRegion declared in global_nvs.asl. */
if (gnvs_size < 0x100)
gnvs_size = 0x100;
if (gnvs_size > 0x1000)
gnvs_size = 0x2000;
else if (CONFIG(MAINBOARD_HAS_CHROMEOS))
gnvs_size = 0x1000;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size);
if (!gnvs)
return NULL;
@ -63,7 +72,7 @@ void *gnvs_get_or_create(void)
gnvs_assign_cbmc();
if (CONFIG(CHROMEOS))
gnvs_assign_chromeos();
gnvs_assign_chromeos((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
return gnvs;
}

12
src/acpi/nvs.c
View File

@ -13,15 +13,3 @@ uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs)
{
return &gnvs->cbmc;
}
/* Some <soc/nvs.h> have no chromeos entry. */
void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
{
#if CONFIG(BOARD_EMULATION_QEMU_X86_Q35)
return NULL;
#elif CONFIG(MAINBOARD_HAS_CHROMEOS)
return &gnvs->chromeos;
#else
return NULL;
#endif
}

3
src/include/acpi/acpi_gnvs.h
View File

@ -8,14 +8,13 @@
void *acpi_get_gnvs(void);
void *gnvs_get_or_create(void);
void gnvs_assign_chromeos(void);
void gnvs_assign_chromeos(void *gnvs_section);
void gnvs_set_ecfw_rw(void);
/* Platform code must implement these. */
struct global_nvs;
size_t gnvs_size_of_array(void);
uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs);
void *gnvs_chromeos_ptr(struct global_nvs *gnvs);
/*
* These functions populate the gnvs structure in acpi table.

8
src/soc/amd/picasso/include/soc/nvs.h
View File

@ -9,9 +9,7 @@
#ifndef AMD_PICASSO_NVS_H
#define AMD_PICASSO_NVS_H
#include <commonlib/helpers.h>
#include <stdint.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/southbridge.h>
struct __packed global_nvs {
@ -25,12 +23,6 @@ struct __packed global_nvs {
uint8_t tmps; /* 0x17 - Temperature Sensor ID */
uint8_t tcrt; /* 0x18 - Critical Threshold */
uint8_t tpsv; /* 0x19 - Passive Threshold */
uint8_t unused[230];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
};
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* AMD_PICASSO_NVS_H */

8
src/soc/amd/stoneyridge/include/soc/nvs.h
View File

@ -9,9 +9,7 @@
#ifndef __SOC_STONEYRIDGE_NVS_H__
#define __SOC_STONEYRIDGE_NVS_H__
#include <commonlib/helpers.h>
#include <stdint.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/southbridge.h>
struct __packed global_nvs {
@ -32,12 +30,6 @@ struct __packed global_nvs {
uint32_t fw01; /* 0x28 - XhciFwRamAddr_Rom, Boot RAM sz/base */
uint32_t fw03; /* 0x2c - XhciFwRomAddr_Ram, Instr RAM sz/base */
uint32_t eh10; /* 0x30 - EHCI BAR */
uint8_t unused[204];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
};
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* __SOC_STONEYRIDGE_NVS_H__ */

8
src/soc/intel/apollolake/include/soc/nvs.h
View File

@ -10,8 +10,6 @@
#define _SOC_APOLLOLAKE_NVS_H_
#include <stdint.h>
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/gnvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@ -35,12 +33,6 @@ struct __packed global_nvs {
uint64_t elng; /* 0x35 - 0x3C EPC Length */
uint64_t a4gb; /* 0x3D - 0x44 Base of above 4GB MMIO Resource */
uint64_t a4gs; /* 0x45 - 0x4C Length of above 4GB MMIO Resource */
uint8_t unused[179];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
};
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _SOC_APOLLOLAKE_NVS_H_ */

6
src/soc/intel/baytrail/include/soc/nvs.h
View File

@ -4,8 +4,6 @@
#define _BAYTRAIL_NVS_H_
#include <stdint.h>
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/device_nvs.h>
struct __packed global_nvs {
@ -50,12 +48,10 @@ struct __packed global_nvs {
u8 unused[76];
/* ChromeOS specific (0x100-0xfff) */
chromeos_acpi_t chromeos;
u8 chromeos_reserve[0xf00];
/* Baytrail LPSS (0x1000) */
device_nvs_t dev;
};
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _BAYTRAIL_NVS_H_ */

6
src/soc/intel/braswell/include/soc/nvs.h
View File

@ -4,9 +4,7 @@
#define _SOC_NVS_H_
#include <stdint.h>
#include <commonlib/helpers.h>
#include <soc/device_nvs.h>
#include <vendorcode/google/chromeos/gnvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@ -52,12 +50,10 @@ struct __packed global_nvs {
u8 unused[76];
/* ChromeOS specific (0x100-0xfff) */
chromeos_acpi_t chromeos;
u8 chromeos_reserve[0xf00];
/* LPSS (0x1000) */
device_nvs_t dev;
};
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _SOC_NVS_H_ */

6
src/soc/intel/broadwell/include/soc/nvs.h
View File

@ -4,9 +4,7 @@
#define _BROADWELL_NVS_H_
#include <stdint.h>
#include <commonlib/helpers.h>
#include <soc/device_nvs.h>
#include <vendorcode/google/chromeos/gnvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@ -42,12 +40,10 @@ struct __packed global_nvs {
u8 unused2[76];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
u8 chromeos_reserve[0xf00];
/* Device specific (0x1000) */
device_nvs_t dev;
};
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif

8
src/soc/intel/common/block/include/intelblocks/nvs.h
View File

@ -4,8 +4,6 @@
#define SOC_INTEL_COMMON_BLOCK_NVS_H
#include <stdint.h>
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/gnvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@ -28,12 +26,6 @@ struct __packed global_nvs {
u8 uior; /* 0x2f - UART debug controller init on S3 resume */
u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */
u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */
u8 unused[192];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
};
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif

8
src/soc/intel/skylake/include/soc/nvs.h
View File

@ -4,8 +4,6 @@
#define _SOC_NVS_H_
#include <stdint.h>
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/gnvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@ -48,12 +46,6 @@ struct __packed global_nvs {
u64 elng; /* 0x4C - 0x53 EPC Length */
u64 a4gb; /* 0x54 - 0x5B Base of above 4GB MMIO Resource */
u64 a4gs; /* 0x5C - 0x63 Length of above 4GB MMIO Resource */
u8 rsvd[156];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
};
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif

8
src/southbridge/intel/bd82x6x/include/soc/nvs.h
View File

@ -3,9 +3,7 @@
#ifndef SOUTHBRIDGE_INTEL_BD82X6X_NVS_H
#define SOUTHBRIDGE_INTEL_BD82X6X_NVS_H
#include <commonlib/helpers.h>
#include <stdint.h>
#include "vendorcode/google/chromeos/gnvs.h"
struct __packed global_nvs {
/* Miscellaneous */
@ -103,12 +101,6 @@ struct __packed global_nvs {
u8 tpiq; /* 0xf5 - trackpad IRQ value */
u32 cbmc;
u8 rsvd13[6]; /* 0xfa - rsvd */
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
};
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_NVS_H */

1
src/southbridge/intel/i82801gx/include/soc/nvs.h
View File

@ -98,7 +98,6 @@ struct __packed global_nvs {
u8 bten;
u32 cbmc;
u8 rsvd13[10];
};
#endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */

1
src/southbridge/intel/i82801ix/include/soc/nvs.h
View File

@ -98,7 +98,6 @@ struct __packed global_nvs {
u8 bten;
u32 cbmc;
u8 rsvd13[10];
};
#endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */

1
src/southbridge/intel/i82801jx/include/soc/nvs.h
View File

@ -97,7 +97,6 @@ struct __packed global_nvs {
u8 bten;
u32 cbmc;
u8 rsvd13[10];
};
#endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */

1
src/southbridge/intel/ibexpeak/include/soc/nvs.h
View File

@ -100,7 +100,6 @@ struct __packed global_nvs {
u8 xhci;
u32 cbmc;
u8 rsvd13[72]; /* rsvd */
};
#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */

8
src/southbridge/intel/lynxpoint/include/soc/nvs.h
View File

@ -3,9 +3,7 @@
#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H
#define SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H
#include <commonlib/helpers.h>
#include <stdint.h>
#include "vendorcode/google/chromeos/gnvs.h"
struct __packed global_nvs {
/* Miscellaneous */
@ -75,12 +73,6 @@ struct __packed global_nvs {
u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */
u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */
u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */
u8 rsvd6[92];
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
};
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */

5
src/vendorcode/google/chromeos/gnvs.h
View File

@ -10,10 +10,7 @@
/*
* chromeos_acpi_t portion of ACPI GNVS is assumed to live at
* 0x100 - 0x1000. When defining global_nvs, use check_member
* to ensure that it is properly aligned:
*
* check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
* 0x100 - 0x1000.
*/
#define GNVS_CHROMEOS_ACPI_OFFSET 0x100