soc/intel/cmn/cpu: API to set TME core activation

This patch implements API to program TME core activation MSR 0x9FF.

Write zero to TME core activate MSR will translate the
TME_ACTIVATE[MK_TME_KEYID_BITS] value into PMH mask register.

Note: TME_ACTIVATE[MK_TME_KEYID_BITS] = MSR 0x982 Bits[32-35]

TEST=Able to build and boot Google/Redrix.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I48cf8e255b294828ac683ab96eb61ad86578e852
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>

src/soc/intel/common/block/cpu/cpulib.c

@@ -510,3 +510,10 @@ bool is_tme_supported(void)
 
 	return (cpuid_regs.ecx & TME_SUPPORTED);
 }
+
+void set_tme_core_activate(void)
+{
+	msr_t msr = { .lo = 0, .hi = 0 };
+
+	wrmsr(MSR_CORE_MKTME_ACTIVATION, msr);
+}

src/soc/intel/common/block/include/intelblocks/cpulib.h

@@ -202,4 +202,13 @@ void init_core_prmrr(void);
  */
 bool is_tme_supported(void);
 
+/*
+ * Set TME core activate MSR
+ *
+ * Write zero to TME core activate MSR will translate the TME_ACTIVATE[MK_TME_KEYID_BITS]
+ * value into PMH mask register.
+ * TME_ACTIVATE[MK_TME_KEYID_BITS] = MSR 0x982 Bits[32-35]
+ */
+void set_tme_core_activate(void);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_CPULIB_H */

src/soc/intel/common/block/include/intelblocks/msr.h

@@ -94,6 +94,8 @@
 #define PKG_POWER_LIMIT_TIME_MASK	(0x7f)
 #define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24
 #define PKG_POWER_LIMIT_DUTYCYCLE_MASK  (0x7f)
+
+#define MSR_CORE_MKTME_ACTIVATION	0x9ff
 /* SMM save state MSRs */
 #define SMBASE_MSR			0xc20
 #define IEDBASE_MSR			0xc22