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CAR simplifications, typos, readability improvements (trivial). 

- Use some more #defines instead of hard-coding values.

 - Merge multiple movl/orl or movl/andl lines into one where possible.

 - Add some TODOs in places which seem to have either an incorrect
   code or incorrect comment.

 - Fix typos: s/for/from/, s/BSC/BSP/, s/size/carsize/.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-10-01 07:27:51 +00:00
parent 52000e1688
commit 66d1687b92
4 changed files with 35 additions and 41 deletions
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19
src/cpu/amd/car/cache_as_ram.inc
View File

@ -90,7 +90,7 @@ cache_as_ram_setup:
*/ */
movl $0x1b, %ecx movl $0x1b, %ecx
rdmsr rdmsr
bt $8, %eax /* BSC */ bt $8, %eax /* BSP */
jnc CAR_FAM10_out jnc CAR_FAM10_out
/* Enable RT tables on BSP. */ /* Enable RT tables on BSP. */
@ -135,15 +135,14 @@ CAR_FAM10_out:
wrmsr wrmsr
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
/* Set MMIO Config space BAR. */ /* Set MMIO config space BAR. */
movl $MSR_MCFG_BASE, %ecx movl $MSR_MCFG_BASE, %ecx
rdmsr rdmsr
andl $(~(0xfff00000 | (0xf << 2))), %eax andl $(~(0xfff00000 | (0xf << 2))), %eax
orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000) | (8 << 2) | (1 << 0)), %eax orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000), %eax
orl $((8 << 2) | (1 << 0)), %eax
andl $(~(0x0000ffff)), %edx andl $(~(0x0000ffff)), %edx
orl $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx orl $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx
wrmsr wrmsr
#endif #endif
@ -216,7 +215,7 @@ clear_fixed_var_mtrr_out:
.endm .endm
/* /*
* size is the cache size in bytes we want to use for CAR. * carsize is the cache size in bytes we want to use for CAR.
* windowoffset is the 32k-aligned window into CAR size. * windowoffset is the 32k-aligned window into CAR size.
*/ */
.macro simplemask carsize, windowoffset .macro simplemask carsize, windowoffset
@ -289,7 +288,7 @@ wbcache_post_fam10_setup:
/* Set the default memory type and enable fixed and variable MTRRs. */ /* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */ movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
wrmsr wrmsr
/* Enable the MTRRs and IORRs in SYSCFG. */ /* Enable the MTRRs and IORRs in SYSCFG. */
@ -302,7 +301,7 @@ wbcache_post_fam10_setup:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff, %eax andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0 movl %eax, %cr0
jmp_if_k8(fam10_end_part1) jmp_if_k8(fam10_end_part1)
@ -310,7 +309,7 @@ wbcache_post_fam10_setup:
/* So we need to check if it is BSP. */ /* So we need to check if it is BSP. */
movl $0x1b, %ecx movl $0x1b, %ecx
rdmsr rdmsr
bt $8, %eax /* BSC */ bt $8, %eax /* BSP */
jnc CAR_FAM10_ap jnc CAR_FAM10_ap
fam10_end_part1: fam10_end_part1:
@ -365,7 +364,7 @@ CAR_FAM10_ap:
movl $0xc001001f, %ecx /* NB_CFG_MSR */ movl $0xc001001f, %ecx /* NB_CFG_MSR */
rdmsr rdmsr
movl %edi, %ecx /* CoreID bits */ movl %edi, %ecx /* CoreID bits */
bt $(54-32), %edx bt $(54 - 32), %edx
jc roll_cfg jc roll_cfg
rolb %cl, %bl rolb %cl, %bl
roll_cfg: roll_cfg:

13
src/cpu/intel/car/cache_as_ram.inc
View File

@ -110,7 +110,7 @@ NotHtProcessor:
/* Set the default memory type and enable fixed and variable MTRRs. */ /* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */ movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
wrmsr wrmsr
/* Clear all MTRRs. */ /* Clear all MTRRs. */
@ -169,7 +169,7 @@ clear_fixed_var_mtrr_out:
.endm .endm
/* /*
* size is the cache size in bytes we want to use for CAR. * carsize is the cache size in bytes we want to use for CAR.
* windowoffset is the 32k-aligned window into CAR size. * windowoffset is the 32k-aligned window into CAR size.
*/ */
.macro simplemask carsize, windowoffset .macro simplemask carsize, windowoffset
@ -221,8 +221,7 @@ clear_fixed_var_mtrr_out:
*/ */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $REAL_XIP_ROM_BASE, %eax movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx
@ -233,7 +232,7 @@ clear_fixed_var_mtrr_out:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff, %eax andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0 movl %eax, %cr0
/* Read the range with lodsl. */ /* Read the range with lodsl. */
@ -303,7 +302,7 @@ lout:
pushl %eax /* BIST */ pushl %eax /* BIST */
call main call main
/* We don't need CAR for now on. */ /* We don't need CAR from now on. */
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
@ -332,7 +331,7 @@ lout:
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff, %eax andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0 movl %eax, %cr0
/* Clear boot_complete flag. */ /* Clear boot_complete flag. */

41
src/cpu/via/car/cache_as_ram.inc
View File

@ -45,7 +45,7 @@ CacheAsRam:
/* Set the default memory type and enable fixed and variable MTRRs. */ /* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */ movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
wrmsr wrmsr
/* Clear all MTRRs. */ /* Clear all MTRRs. */
@ -100,8 +100,7 @@ clear_fixed_var_mtrr_out:
*/ */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $REAL_XIP_ROM_BASE, %eax movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx
@ -109,13 +108,16 @@ clear_fixed_var_mtrr_out:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr wrmsr
/* Set the default memory type and enable fixed and variable MTRRs. */
/* TODO: Or also enable fixed MTRRs? Bug in the code? */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $0x00000800, %eax /* Enable variable and fixed MTRRs. */ movl $(MTRRdefTypeEn), %eax
wrmsr wrmsr
/* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff, %eax andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0 movl %eax, %cr0
/* Read the range with lodsl. */ /* Read the range with lodsl. */
@ -186,27 +188,24 @@ testok:
* want to go back. * want to go back.
*/ */
/* We don't need CAR for now on. */ /* We don't need CAR from now on. */
/* Disable cache. */ /* Disable cache. */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30), %eax orl $(1 << 30), %eax
movl %eax, %cr0 movl %eax, %cr0
/* /* Set the default memory type and enable variable MTRRs. */
* Set the default memory type and disable fixed and enable /* TODO: Or also enable fixed MTRRs? Bug in the code? */
* variable MTRRs.
*/
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $0x00000800, %eax /* Enable variable & disable fixed MTRRs. */ movl $(MTRRdefTypeEn), %eax
wrmsr wrmsr
/* Enable caching for first 1M using variable MTRR. */ /* Enable caching for first 1M using variable MTRR. */
movl $MTRRphysBase_MSR(0), %ecx movl $MTRRphysBase_MSR(0), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(0 | 6), %eax movl $(0 | MTRR_TYPE_WRBACK), %eax
// movl $(0 | MTRR_TYPE_WRBACK), %eax
wrmsr wrmsr
/* /*
@ -223,8 +222,7 @@ testok:
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(0x80000 | 6), %eax movl $(0x80000 | MTRR_TYPE_WRBACK), %eax
orl $(0 | 6), %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx
@ -234,8 +232,7 @@ testok:
movl $MTRRphysBase_MSR(2), %ecx movl $MTRRphysBase_MSR(2), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(0xc0000 | 6), %eax movl $(0xc0000 | MTRR_TYPE_WRBACK), %eax
orl $(0 | 6), %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(2), %ecx movl $MTRRphysMask_MSR(2), %ecx
@ -246,21 +243,17 @@ testok:
/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
movl $MTRRphysBase_MSR(3), %ecx movl $MTRRphysBase_MSR(3), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $REAL_XIP_ROM_BASE,%eax movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
orl $(0 | 6), %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(3), %ecx movl $MTRRphysMask_MSR(3), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $CONFIG_XIP_ROM_SIZE, %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
decl %eax
notl %eax
orl $(0 | 0x800), %eax
wrmsr wrmsr
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff, %eax andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0 movl %eax, %cr0
invd invd

3
src/include/cpu/x86/mtrr.h
View File

@ -15,6 +15,9 @@
#define MTRRcap_MSR 0x0fe #define MTRRcap_MSR 0x0fe
#define MTRRdefType_MSR 0x2ff #define MTRRdefType_MSR 0x2ff
#define MTRRdefTypeEn (1 << 11)
#define MTRRdefTypeFixEn (1 << 10)
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)