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src/soc/intel/cannonlake: Update C-state latency control limits 

PC10 is a necessary condition for S0ix entry. With the current C-state limits,
CPU fails to enter PC10 during S0ix. C-state Latency control limits
have to be tuned to new values for PC10 entry.

Change-Id: I0f5227f9c3c10c5a9e335ab118eb0ec185445374
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/23220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Vaibhav Shankar 2018-01-11 10:27:50 -08:00 committed by Martin Roth
parent 73f19dca38
commit 66dbb0c5d6
2 changed files with 12 additions and 17 deletions
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15
src/soc/intel/cannonlake/cpu.c
View File

@ -136,36 +136,31 @@ static void configure_c_states(void)
{
msr_t msr;
/* C-state Interrupt Response Latency Control 0 - package C3 latency */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr);
/* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
/* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
/* C-state Interrupt Response Latency Control 3 - package C8 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS |
msr.lo = IRTL_VALID | IRTL_32768_NS |
C_STATE_LATENCY_CONTROL_3_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
/* C-state Interrupt Response Latency Control 4 - package C9 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS |
msr.lo = IRTL_VALID | IRTL_32768_NS |
C_STATE_LATENCY_CONTROL_4_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
/* C-state Interrupt Response Latency Control 5 - package C10 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS |
msr.lo = IRTL_VALID | IRTL_32768_NS |
C_STATE_LATENCY_CONTROL_5_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}

14
src/soc/intel/cannonlake/include/soc/cpu.h
View File

@ -21,13 +21,13 @@
#include <device/device.h>
#include <intelblocks/msr.h>
/* Latency times in units of 1024ns. */
#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e
#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76
#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x94
#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xfa
#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x14c
#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x3f2
/* Latency times in units of 32768ns */
#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d
#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d
#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d
#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d
#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d
#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d
/* Power in units of mW */
#define C1_POWER 0x3e8