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Documentation: x86 Enable Serial Output 

Document the steps necessary to enable serial output

TEST=None

Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13444
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2016-02-04 11:21:33 -08:00 committed by Leroy P Leahy
parent 7e0078b990
commit 66decf1644
4 changed files with 111 additions and 0 deletions
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25
Documentation/Intel/Board/board.html
View File

@ -14,6 +14,7 @@
</p> </p>
<ol> <ol>
<li><a href="#RequiredFiles">Required Files</a></li> <li><a href="#RequiredFiles">Required Files</a></li>
<li>Enable <a href="#SerialOutput">Serial Output</a></li>
</ol> </ol>
@ -77,6 +78,30 @@
</ol> </ol>
<hr>
<h1><a name="SerialOutput">Enable Serial Output</a></h1>
<p>
Use the following steps to enable serial output:
</p>
<ol>
<li>Implement the car_mainboard_pre_console_init routine in the com_init.c
file:
<ol type="A">
<li>Power on and enable the UART controller</li>
<li>Connect the UART receive and transmit data lines to the
appropriate SoC pins
</li>
</ol>
</li>
<li>Add Makefile.inc
<ol type="A">
<li>Add com_init.c to romstage</li>
</ol>
</li>
</ol>
<hr> <hr>
<p>Modified: 31 January 2016</p> <p>Modified: 31 January 2016</p>
</body> </body>

44
Documentation/Intel/SoC/soc.html
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@ -19,6 +19,11 @@
<li><a href="#EarlyDebug">Early Debug</a></li> <li><a href="#EarlyDebug">Early Debug</a></li>
<li><a href="#Bootblock">Bootblock</a></li> <li><a href="#Bootblock">Bootblock</a></li>
<li><a href="#TempRamInit">TempRamInit</a></li> <li><a href="#TempRamInit">TempRamInit</a></li>
<li><a href="#Romstage">Romstage</a>
<ol type="A">
<li>Enable <a href="#SerialOutput">Serial Output"</a></li>
</ol>
</li>
</ol> </ol>
@ -284,6 +289,45 @@ Use the following steps to debug the call to TempRamInit:
</ol> </ol>
<hr>
<h1><a name="Romstage">Romstage</a></h1>
<h2><a name="SerialOutput">Serial Output</a></h2>
<p>
The following steps add the serial output support for romstage:
</p>
<ol>
<li>Create the romstage subdirectory</li>
<li>Add romstage/romstage.c
<ol type="A">
<li>Program the necessary base addresses</li>
<li>Disable the TCO</li>
</ol>
</li>
<li>Add romstage/Makefile.inc
<ol type="A">
<li>Add romstage.c to romstage</li>
</ol>
</li>
<li>Add gpio configuration support if necessary</li>
<li>Add the necessary .h files to support the build</li>
<li>Update Makefile.inc
<ol type="A">
<li>Add the romstage subdirectory</li>
<li>Add the gpio configuration support file to romstage</li>
</ol>
</li>
<li>Set the necessary Kconfig values to enable serial output:
<ul>
<li>CONFIG_DRIVERS_UART_&lt;driver&gt;=y</li>
<li>CONFIG_CONSOLE_SERIAL=y</li>
<li>CONFIG_UART_FOR_CONSOLE=&lt;port&gt;</li>
<li>CONFIG_CONSOLE_SERIAL_115200=y</li>
</ul>
</li>
</ol>
<hr> <hr>
<p>Modified: 31 January 2016</p> <p>Modified: 31 January 2016</p>
</body> </body>

28
Documentation/Intel/development.html
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@ -71,6 +71,17 @@
<li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li>
<li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li>
<li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li> <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li>
<li>Enable the serial port
<ol type="A">
<li>Power on, enable and configure GPIOs for the
<a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a>
</li>
<li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a>
support to romstage
</li>
</ol>
</li>
<li>Enable <a target="_blank" href="fsp1_1.html#corebootFspDebugging">coreboot/FSP</a> debugging</li>
</ol> </ol>
@ -106,6 +117,23 @@
Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
</td> </td>
</tr> </tr>
<tr bgcolor="#c0ffc0">
<th>Board</th>
<th>Where</th>
<th>Testing</th>
</tr>
<tr>
<td>Serial Port</td>
<td>
SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br>
Enable: src/soc/mainboard/&lt;Board&gt;/com_init.c/<a target="_blank" href="Board/board.html#SerialOutput">car_mainboard_pre_console_init</a>
</td>
<td>Debug serial output works</td>
</tr>
<tr bgcolor="#c0ffc0"> <tr bgcolor="#c0ffc0">
<th>FSP</th> <th>FSP</th>
<th>Where</th> <th>Where</th>

14
Documentation/Intel/fsp1_1.html
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@ -15,6 +15,7 @@
<ol> <ol>
<li><a href="#RequiredFiles">Required Files</a></li> <li><a href="#RequiredFiles">Required Files</a></li>
<li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li> <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li>
<li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li>
</ol> </ol>
<p> <p>
@ -57,6 +58,19 @@
</p> </p>
<hr>
<h1><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h1>
<p>
Set the following Kconfig values:
</p>
<ul>
<li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li>
<li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li>
<li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li>
<li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li>
</ul>
<hr> <hr>
<p>Modified: 31 January 2016</p> <p>Modified: 31 January 2016</p>
</body> </body>