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cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS 

CPU_MICROCODE_IN_CBFS was designed to mean that loading microcode updates
from a CBFS file is supported, however, the name implies that microcode is
present in CBFS. This has recently caused confusion both with contributions
from Google, as well as SAGE. Rename this option to
SUPPORT_CPU_UCODE_IN_CBFS in order to make it clearer that what is meant is
"hey, the code we have for this CPU supports loading microcode updates from
CBFS", and prevent further confusion.

Change-Id: I394555f690b5ab4cac6fbd3ddbcb740ab1138339
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4482
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Alexandru Gagniuc 2013-12-04 22:21:15 -06:00
parent 580d11f1f1
commit 66e0c4c8c4
9 changed files with 16 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/cpu/Kconfig
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@ -73,7 +73,7 @@ config SSE2
endif # ARCH_X86 endif # ARCH_X86
config CPU_MICROCODE_IN_CBFS config SUPPORT_CPU_UCODE_IN_CBFS
bool bool
default n default n
@ -90,9 +90,8 @@ config CPU_MICROCODE_ADDED_DURING_BUILD
choice choice
prompt "Include CPU microcode in CBFS" if ARCH_X86 prompt "Include CPU microcode in CBFS" if ARCH_X86
default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS
default CPU_MICROCODE_CBFS_EXTERNAL if CPU_MICROCODE_IN_CBFS default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS
default CPU_MICROCODE_CBFS_NONE
config CPU_MICROCODE_CBFS_GENERATE config CPU_MICROCODE_CBFS_GENERATE
bool "Generate from tree" bool "Generate from tree"

6
src/cpu/intel/fsp_model_206ax/Kconfig
View File

@ -32,7 +32,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2 select SSE2
select UDELAY_LAPIC select UDELAY_LAPIC
select SMM_TSEG select SMM_TSEG
select CPU_MICROCODE_IN_CBFS if HAVE_FSP_BIN select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
config BOOTBLOCK_CPU_INIT config BOOTBLOCK_CPU_INIT
@ -53,12 +53,12 @@ config ENABLE_VMX
config CPU_MICROCODE_CBFS_LOC config CPU_MICROCODE_CBFS_LOC
hex hex
depends on CPU_MICROCODE_IN_CBFS depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xfff70000 default 0xfff70000
config CPU_MICROCODE_CBFS_LEN config CPU_MICROCODE_CBFS_LEN
hex hex
depends on CPU_MICROCODE_IN_CBFS depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xC000 if CPU_INTEL_FSP_MODEL_306AX default 0xC000 if CPU_INTEL_FSP_MODEL_306AX
default 0x2800 if CPU_INTEL_FSP_MODEL_206AX default 0x2800 if CPU_INTEL_FSP_MODEL_206AX

2
src/cpu/intel/fsp_model_206ax/microcode_blob.c
View File

@ -18,7 +18,7 @@
*/ */
unsigned microcode[] = { unsigned microcode[] = {
#if IS_ENABLED(CONFIG_CPU_MICROCODE_IN_CBFS) #if IS_ENABLED(SUPPORT_CPU_UCODE_IN_CBFS)
#include "microcode_blob.h" #include "microcode_blob.h"
#endif #endif
}; };

2
src/cpu/intel/haswell/Kconfig
View File

@ -14,7 +14,7 @@ config CPU_SPECIFIC_OPTIONS
select SMM_MODULES select SMM_MODULES
select RELOCATABLE_MODULES select RELOCATABLE_MODULES
select DYNAMIC_CBMEM select DYNAMIC_CBMEM
select CPU_MICROCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
#select AP_IN_SIPI_WAIT #select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE

8
src/cpu/intel/microcode/microcode.c
View File

@ -30,11 +30,11 @@
#include <cpu/intel/microcode.h> #include <cpu/intel/microcode.h>
#ifdef __PRE_RAM__ #ifdef __PRE_RAM__
#if CONFIG_CPU_MICROCODE_IN_CBFS #if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS
#include <arch/cbfs.h> #include <arch/cbfs.h>
#endif #endif
#else #else
#if CONFIG_CPU_MICROCODE_IN_CBFS #if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS
#include <cbfs.h> #include <cbfs.h>
#endif #endif
#include <smp/spinlock.h> #include <smp/spinlock.h>
@ -82,7 +82,7 @@ static inline u32 read_microcode_rev(void)
return msr.hi; return msr.hi;
} }
#if CONFIG_CPU_MICROCODE_IN_CBFS #if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS
#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" #define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
@ -192,7 +192,7 @@ void intel_update_microcode_from_cbfs(void)
#endif #endif
} }
#else /* !CONFIG_CPU_MICROCODE_IN_CBFS */ #else /* !CONFIG_SUPPORT_CPU_UCODE_IN_CBFS */
void intel_update_microcode(const void *microcode_updates) void intel_update_microcode(const void *microcode_updates)
{ {

2
src/cpu/intel/model_2065x/Kconfig
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@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_CONSTANT_RATE select TSC_CONSTANT_RATE
select SMM_TSEG select SMM_TSEG
select HAVE_INIT_TIMER select HAVE_INIT_TIMER
select CPU_MICROCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
#select AP_IN_SIPI_WAIT #select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE

2
src/cpu/intel/model_206ax/Kconfig
View File

@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2 select SSE2
select UDELAY_LAPIC select UDELAY_LAPIC
select SMM_TSEG select SMM_TSEG
select CPU_MICROCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
#select AP_IN_SIPI_WAIT #select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE

2
src/cpu/via/nano/Kconfig
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@ -28,7 +28,7 @@ config CPU_SPECIFIC_OPTIONS
select MMX select MMX
select SSE2 select SSE2
select CACHE_AS_RAM select CACHE_AS_RAM
select CPU_MICROCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
config DCACHE_RAM_BASE config DCACHE_RAM_BASE
hex hex

2
src/include/cpu/intel/microcode.h
View File

@ -21,7 +21,7 @@
#define __CPU__INTEL__MICROCODE__ #define __CPU__INTEL__MICROCODE__
#ifndef __PRE_RAM__ #ifndef __PRE_RAM__
#if CONFIG_CPU_MICROCODE_IN_CBFS #if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS
void intel_update_microcode_from_cbfs(void); void intel_update_microcode_from_cbfs(void);
/* Find a microcode that matches the revision and platform family returning /* Find a microcode that matches the revision and platform family returning
* NULL if none found. */ * NULL if none found. */