mb/dell/snb_ivb_workstations: Add Precision T1650 support
Precision is a Mid Tower chassis platform with very similar mainboard to OptiPlex 9010. It has one more PCIe port and a PCI port. It also incorporates C216 chipset instead of Q77 and enables DRAM ECC support. Other changes are related to subsystem ID and fan control initialization. TEST=Boot Dell Precision T1650 and launch Debian 10. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I4ec2013d5f53af36cab0d1def19272f5ef1a9516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Michał Żygowski
parent
7e8b597093
commit
66f99f7fa7
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@ -28,9 +28,11 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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default "OptiPlex 9010" if BOARD_DELL_OPTIPLEX_9010
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default "Precision T1650" if BOARD_DELL_PRECISION_T1650
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config VARIANT_DIR
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default "optiplex_9010_sff" if BOARD_DELL_OPTIPLEX_9010
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default "precision_t1650" if BOARD_DELL_PRECISION_T1650
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config DEVICETREE
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default "variants/baseboard/devicetree.cb"
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@ -2,3 +2,8 @@ config BOARD_DELL_OPTIPLEX_9010
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bool "OptiPlex 9010 SFF"
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select BOARD_DELL_SNB_IVB_WORKSTATIONS
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select SOUTHBRIDGE_INTEL_BD82X6X
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config BOARD_DELL_PRECISION_T1650
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bool "Dell Precision T1650"
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select BOARD_DELL_SNB_IVB_WORKSTATIONS
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select SOUTHBRIDGE_INTEL_C216
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Binary file not shown.
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@ -0,0 +1,36 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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0x10ec0269, /* Codec Vendor / Device ID: Realtek */
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0x1028053a, /* Subsystem ID */
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11, /* Number of 4 dword sets */
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AZALIA_SUBVENDOR(0, 0x1028053a),
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AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x14, 0x99130110),
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AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x18, 0x02a19830),
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AZALIA_PIN_CFG(0, 0x19, 0x01a19840),
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AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x1b, 0x01014020),
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AZALIA_PIN_CFG(0, 0x1d, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x21, 0x0221402f),
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0x80862806, /* Codec Vendor / Device ID: Intel */
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0x80860101, /* Subsystem ID */
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4, /* Number of 4 dword sets */
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AZALIA_SUBVENDOR(3, 0x80860101),
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AZALIA_PIN_CFG(3, 0x05, 0x18560010),
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AZALIA_PIN_CFG(3, 0x06, 0x18560020),
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AZALIA_PIN_CFG(3, 0x07, 0x58560030),
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};
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const u32 pc_beep_verbs[0] = {};
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AZALIA_ARRAY_SIZES;
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@ -0,0 +1,236 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SCH5545_BOARD_EC_TABLE_H
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#define SCH5545_BOARD_EC_TABLE_H
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#include <baseboard/sch5545_ec.h>
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static const ec_chassis_tdp_t ec_hwm_chassis3[] = {
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{ 0x33, 0x0005, TDP_COMMON },
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{ 0x2f, 0x0018, TDP_COMMON },
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{ 0x2f, 0x0019, TDP_COMMON },
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{ 0x2f, 0x001a, TDP_COMMON },
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{ 0x00, 0x0080, TDP_COMMON },
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{ 0x00, 0x0081, TDP_COMMON },
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{ 0xbb, 0x0083, TDP_COMMON },
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{ 0x96, 0x0085, TDP_16 },
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{ 0x41, 0x0086, TDP_16 },
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{ 0x66, 0x008a, TDP_16 },
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{ 0x6b, 0x008b, TDP_16 },
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{ 0x65, 0x0090, TDP_COMMON },
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{ 0x5c, 0x0091, TDP_COMMON },
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{ 0x86, 0x0092, TDP_COMMON },
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{ 0xa4, 0x0096, TDP_COMMON },
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{ 0xa4, 0x0097, TDP_COMMON },
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{ 0xa4, 0x0098, TDP_COMMON },
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{ 0xa4, 0x009b, TDP_COMMON },
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{ 0x0e, 0x00a0, TDP_COMMON },
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{ 0x0e, 0x00a1, TDP_COMMON },
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{ 0x7c, 0x00ae, TDP_COMMON },
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{ 0x86, 0x00af, TDP_COMMON },
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{ 0x95, 0x00b0, TDP_COMMON },
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{ 0x9a, 0x00b3, TDP_COMMON },
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{ 0x08, 0x00b6, TDP_COMMON },
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{ 0x08, 0x00b7, TDP_COMMON },
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{ 0x64, 0x00ea, TDP_COMMON },
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{ 0xff, 0x00ef, TDP_COMMON },
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{ 0x15, 0x00f8, TDP_COMMON },
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{ 0x00, 0x00f9, TDP_COMMON },
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{ 0x30, 0x00f0, TDP_COMMON },
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{ 0x01, 0x00fd, TDP_COMMON },
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{ 0x88, 0x01a1, TDP_COMMON },
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{ 0x08, 0x01a2, TDP_COMMON },
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{ 0x08, 0x01b1, TDP_COMMON },
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{ 0x94, 0x01be, TDP_COMMON },
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{ 0x94, 0x0280, TDP_16 },
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{ 0x11, 0x0281, TDP_16 },
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{ 0x03, 0x0282, TDP_COMMON },
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{ 0x0a, 0x0283, TDP_COMMON },
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{ 0x80, 0x0284, TDP_COMMON },
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{ 0x03, 0x0285, TDP_COMMON },
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{ 0x68, 0x0288, TDP_16 },
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{ 0x10, 0x0289, TDP_16 },
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{ 0x03, 0x028a, TDP_COMMON },
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{ 0x0a, 0x028b, TDP_COMMON },
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{ 0x80, 0x028c, TDP_COMMON },
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{ 0x03, 0x028d, TDP_COMMON },
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};
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static const ec_chassis_tdp_t ec_hwm_chassis4[] = {
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{ 0x33, 0x0005, TDP_COMMON },
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{ 0x2f, 0x0018, TDP_COMMON },
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{ 0x2f, 0x0019, TDP_COMMON },
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{ 0x2f, 0x001a, TDP_COMMON },
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{ 0x00, 0x0080, TDP_COMMON },
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{ 0x00, 0x0081, TDP_COMMON },
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{ 0xbb, 0x0083, TDP_COMMON },
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{ 0x99, 0x0085, TDP_32 },
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{ 0x96, 0x0085, TDP_16 },
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{ 0xbc, 0x0086, TDP_32 },
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{ 0x1c, 0x0086, TDP_16 },
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{ 0x41, 0x008a, TDP_32 },
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{ 0x3d, 0x008a, TDP_16 },
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{ 0x63, 0x008b, TDP_32 },
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{ 0x6b, 0x008b, TDP_16 },
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{ 0x68, 0x0090, TDP_COMMON },
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{ 0x5c, 0x0091, TDP_COMMON },
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{ 0x86, 0x0092, TDP_COMMON },
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{ 0xa4, 0x0096, TDP_COMMON },
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{ 0xa4, 0x0097, TDP_COMMON },
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{ 0xa4, 0x0098, TDP_COMMON },
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{ 0xa4, 0x009b, TDP_COMMON },
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{ 0x0c, 0x00a0, TDP_COMMON },
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{ 0x0c, 0x00a1, TDP_COMMON },
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{ 0x72, 0x00ae, TDP_COMMON },
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{ 0x7c, 0x00af, TDP_COMMON },
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{ 0x9a, 0x00b0, TDP_COMMON },
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{ 0x7c, 0x00b3, TDP_COMMON },
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{ 0x08, 0x00b6, TDP_COMMON },
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{ 0x08, 0x00b7, TDP_COMMON },
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{ 0x64, 0x00ea, TDP_COMMON },
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{ 0xff, 0x00ef, TDP_COMMON },
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{ 0x15, 0x00f8, TDP_COMMON },
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{ 0x00, 0x00f9, TDP_COMMON },
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{ 0x30, 0x00f0, TDP_COMMON },
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{ 0x01, 0x00fd, TDP_COMMON },
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{ 0x88, 0x01a1, TDP_COMMON },
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{ 0x08, 0x01a2, TDP_COMMON },
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{ 0x08, 0x01b1, TDP_COMMON },
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{ 0x90, 0x01be, TDP_COMMON },
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{ 0x94, 0x0280, TDP_32 },
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{ 0x11, 0x0281, TDP_32 },
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{ 0x68, 0x0280, TDP_16 },
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{ 0x10, 0x0281, TDP_16 },
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{ 0x03, 0x0282, TDP_COMMON },
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{ 0x0a, 0x0283, TDP_COMMON },
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{ 0x80, 0x0284, TDP_COMMON },
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{ 0x03, 0x0285, TDP_COMMON },
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{ 0xa0, 0x0288, TDP_32 },
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{ 0x0f, 0x0289, TDP_32 },
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{ 0xd8, 0x0288, TDP_16 },
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{ 0x0e, 0x0289, TDP_16 },
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{ 0x03, 0x028a, TDP_COMMON },
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{ 0x0a, 0x028b, TDP_COMMON },
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{ 0x80, 0x028c, TDP_COMMON },
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{ 0x03, 0x028d, TDP_COMMON },
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};
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static const ec_chassis_tdp_t ec_hwm_chassis5[] = {
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{ 0x33, 0x0005, TDP_COMMON },
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{ 0x2f, 0x0018, TDP_COMMON },
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{ 0x2f, 0x0019, TDP_COMMON },
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{ 0x2f, 0x001a, TDP_COMMON },
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{ 0x00, 0x0080, TDP_COMMON },
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{ 0x00, 0x0081, TDP_COMMON },
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{ 0xbb, 0x0083, TDP_COMMON },
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{ 0x96, 0x0085, TDP_COMMON },
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{ 0xbc, 0x0086, TDP_16 },
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{ 0x9c, 0x0086, TDP_32 },
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{ 0x39, 0x008a, TDP_32 },
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{ 0x41, 0x008a, TDP_16 },
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{ 0x63, 0x008b, TDP_32 },
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{ 0x6b, 0x008b, TDP_16 },
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{ 0x5c, 0x0091, TDP_COMMON },
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{ 0x86, 0x0092, TDP_COMMON },
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{ 0xa4, 0x0096, TDP_COMMON },
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{ 0xa4, 0x0097, TDP_COMMON },
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{ 0xa4, 0x0098, TDP_COMMON },
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{ 0xa4, 0x009b, TDP_COMMON },
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{ 0x08, 0x00a0, TDP_COMMON },
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{ 0x0c, 0x00a1, TDP_COMMON },
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{ 0x7c, 0x00ae, TDP_COMMON },
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{ 0x7c, 0x00af, TDP_COMMON },
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{ 0x9a, 0x00b0, TDP_COMMON },
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{ 0x7c, 0x00b3, TDP_COMMON },
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{ 0x08, 0x00b6, TDP_COMMON },
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{ 0x08, 0x00b7, TDP_COMMON },
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{ 0x64, 0x00ea, TDP_COMMON },
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{ 0xff, 0x00ef, TDP_COMMON },
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{ 0x15, 0x00f8, TDP_COMMON },
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{ 0x00, 0x00f9, TDP_COMMON },
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{ 0x30, 0x00f0, TDP_COMMON },
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{ 0x01, 0x00fd, TDP_COMMON },
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{ 0x88, 0x01a1, TDP_COMMON },
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{ 0x08, 0x01a2, TDP_COMMON },
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{ 0x08, 0x01b1, TDP_COMMON },
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{ 0x90, 0x01be, TDP_COMMON },
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{ 0x94, 0x0280, TDP_32 },
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{ 0x11, 0x0281, TDP_32 },
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{ 0x3c, 0x0280, TDP_16 },
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{ 0x0f, 0x0281, TDP_16 },
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{ 0x03, 0x0282, TDP_COMMON },
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{ 0x0a, 0x0283, TDP_COMMON },
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{ 0x80, 0x0284, TDP_COMMON },
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{ 0x03, 0x0285, TDP_COMMON },
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{ 0x28, 0x0288, TDP_32 },
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{ 0x0a, 0x0289, TDP_32 },
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{ 0x60, 0x0288, TDP_16 },
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{ 0x09, 0x0289, TDP_16 },
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{ 0x03, 0x028a, TDP_COMMON },
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{ 0x0a, 0x028b, TDP_COMMON },
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{ 0x80, 0x028c, TDP_COMMON },
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{ 0x03, 0x028d, TDP_COMMON },
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};
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static const ec_chassis_tdp_t ec_hwm_chassis6[] = {
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{ 0x33, 0x0005, TDP_COMMON },
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{ 0x2f, 0x0018, TDP_COMMON },
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{ 0x2f, 0x0019, TDP_COMMON },
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{ 0x2f, 0x001a, TDP_COMMON },
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{ 0x00, 0x0080, TDP_COMMON },
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{ 0x00, 0x0081, TDP_COMMON },
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{ 0xbb, 0x0083, TDP_COMMON },
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{ 0x99, 0x0085, TDP_32 },
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{ 0x96, 0x0085, TDP_16 },
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{ 0xec, 0x0086, TDP_32 },
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{ 0x9c, 0x0086, TDP_16 },
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{ 0x39, 0x008a, TDP_32 },
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{ 0x41, 0x008a, TDP_16 },
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{ 0x63, 0x008b, TDP_32 },
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{ 0x6b, 0x008b, TDP_16 },
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{ 0x6d, 0x0090, TDP_COMMON },
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{ 0x5c, 0x0091, TDP_COMMON },
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{ 0x86, 0x0092, TDP_COMMON },
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{ 0xa4, 0x0096, TDP_COMMON },
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{ 0xa4, 0x0097, TDP_COMMON },
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{ 0xa4, 0x0098, TDP_COMMON },
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{ 0xa4, 0x009b, TDP_COMMON },
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{ 0x0e, 0x00a0, TDP_COMMON },
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{ 0x0e, 0x00a1, TDP_COMMON },
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{ 0x7c, 0x00ae, TDP_COMMON },
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{ 0x7c, 0x00af, TDP_COMMON },
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{ 0x98, 0x00b0, TDP_32 },
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{ 0x9a, 0x00b0, TDP_16 },
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{ 0x9a, 0x00b3, TDP_COMMON },
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{ 0x08, 0x00b6, TDP_COMMON },
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{ 0x08, 0x00b7, TDP_COMMON },
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{ 0x64, 0x00ea, TDP_COMMON },
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{ 0xff, 0x00ef, TDP_COMMON },
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{ 0x15, 0x00f8, TDP_COMMON },
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{ 0x00, 0x00f9, TDP_COMMON },
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{ 0x30, 0x00f0, TDP_COMMON },
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{ 0x01, 0x00fd, TDP_COMMON },
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{ 0x88, 0x01a1, TDP_COMMON },
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{ 0x08, 0x01a2, TDP_COMMON },
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{ 0x08, 0x01b1, TDP_COMMON },
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{ 0x97, 0x01be, TDP_32 },
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{ 0x95, 0x01be, TDP_16 },
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{ 0x68, 0x0280, TDP_32 },
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{ 0x10, 0x0281, TDP_32 },
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{ 0xd8, 0x0280, TDP_16 },
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{ 0x0e, 0x0281, TDP_16 },
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{ 0x03, 0x0282, TDP_COMMON },
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{ 0x0a, 0x0283, TDP_COMMON },
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{ 0x80, 0x0284, TDP_COMMON },
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{ 0x03, 0x0285, TDP_COMMON },
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{ 0xe4, 0x0288, TDP_32 },
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{ 0x0c, 0x0289, TDP_32 },
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{ 0x10, 0x0288, TDP_16 },
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{ 0x0e, 0x0289, TDP_16 },
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{ 0x03, 0x028a, TDP_COMMON },
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{ 0x0a, 0x028b, TDP_COMMON },
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{ 0x80, 0x028c, TDP_COMMON },
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{ 0x03, 0x028d, TDP_COMMON },
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};
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#endif // SCH5545_BOARD_EC_TABLE_H
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@ -0,0 +1,21 @@
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chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x1028 0x053a inherit
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chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
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register "sata_port_map" = "0xf"
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device pci 1c.2 on # PCIe Port #3
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smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X"
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end
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device pci 1c.4 on # PCIe Port #5
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X"
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end
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device pci 1c.5 on end # PCIe Port #6
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device pci 1c.6 on end # PCIe Port #7
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device pci 1c.7 on end # PCIe Port #8
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device pci 1e.0 on # PCI bridge
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smbios_slot_desc "SlotTypePci" "SlotLengthLong" "SLOT3" "SlotDataBusWidth32Bit"
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end
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end
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end
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end
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