northbridge/sch: don't overwrite hightables with GPU / TSEG memory
Without this, the hightables are placed just before the end of memory. However we might have the GPU memory located at the exact same spot, that is in the last 4 MiB. So without this patch, this area won't remain marked as "CONFIGURATION TABLES" within coreboot's memory table but becomes "RESERVED" because it is part of the PCI(2,0) device. Change-Id: Ibd111c167c2f6ac03b0ba68581a74ecbd2c9c160 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-on: http://review.coreboot.org/1627 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
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@ -188,7 +188,9 @@ static void pci_domain_set_resources(device_t dev)
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#if CONFIG_WRITE_HIGH_TABLES
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#if CONFIG_WRITE_HIGH_TABLES
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/* Leave some space for ACPI, PIRQ and MP tables. */
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/* Leave some space for ACPI, PIRQ and MP tables. */
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high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
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high_tables_base = tomk * 1024 - HIGH_MEMORY_SIZE;
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high_tables_base -= uma_memory_size;
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high_tables_base -= tseg_memory_base;
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high_tables_size = HIGH_MEMORY_SIZE;
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high_tables_size = HIGH_MEMORY_SIZE;
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#endif
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#endif
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}
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}
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