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northbridge/sch: don't overwrite hightables with GPU / TSEG memory 

Without this, the hightables are placed just before the end of memory.
However we might have the GPU memory located at the exact same spot,
that is in the last 4 MiB. So without this patch, this area won't remain
marked as "CONFIGURATION TABLES" within coreboot's memory table but
becomes "RESERVED" because it is part of the PCI(2,0) device.

Change-Id: Ibd111c167c2f6ac03b0ba68581a74ecbd2c9c160
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1627
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Sebastian Andrzej Siewior 2012-10-26 19:00:22 +02:00 committed by Stefan Reinauer
parent cd02793dff
commit 66fa9e2865
1 changed files with 3 additions and 1 deletions
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4
src/northbridge/intel/sch/northbridge.c
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@ -188,7 +188,9 @@ static void pci_domain_set_resources(device_t dev)
#if CONFIG_WRITE_HIGH_TABLES #if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables. */ /* Leave some space for ACPI, PIRQ and MP tables. */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_base = tomk * 1024 - HIGH_MEMORY_SIZE;
high_tables_base -= uma_memory_size;
high_tables_base -= tseg_memory_base;
high_tables_size = HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE;
#endif #endif
} }