mb/google/rex: Update FMD to support CBFS verification
This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. These blobs were kept separate originally to avoid hash loading and verification every time and hence save boot time. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed. BUG=b:284382452 TEST=Build CB image for google/rex board and test CSE FW update/downgrade with CONFIG_VBOOT_CBFS_INTEGRATION config enabled. Also confirm there is no increase in boot time with this change. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I56865a9e5c8b5f9e908e00e1a7e7e187d5d6a2f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
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@ -8,7 +8,6 @@ FLASH 32M {
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VBLOCK_A 8K
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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RW_FWID_A 64
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ME_RW_A(CBFS) 4000K
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}
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}
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RW_MISC 1M {
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RW_MISC 1M {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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@ -36,7 +35,6 @@ FLASH 32M {
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VBLOCK_B 8K
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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RW_FWID_B 64
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ME_RW_B(CBFS) 4000K
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}
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}
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RW_LEGACY(CBFS) 1M
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RW_LEGACY(CBFS) 1M
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RW_UNUSED 3M
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RW_UNUSED 3M
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@ -8,7 +8,6 @@ FLASH 32M {
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VBLOCK_A 8K
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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RW_FWID_A 64
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ME_RW_A(CBFS) 4000K
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}
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}
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RW_MISC 1M {
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RW_MISC 1M {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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@ -36,7 +35,6 @@ FLASH 32M {
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VBLOCK_B 8K
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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RW_FWID_B 64
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ME_RW_B(CBFS) 4000K
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}
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}
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RW_LEGACY(CBFS) 1M
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RW_LEGACY(CBFS) 1M
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RW_UNUSED 4M
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RW_UNUSED 4M
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@ -8,11 +8,6 @@ FLASH 32M {
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VBLOCK_A 8K
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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RW_FWID_A 64
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#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
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ME_RW_A(CBFS) 4500K
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#else
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ME_RW_A(CBFS) 4400K
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#endif
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}
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}
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# This section starts at the 16M boundary in SPI flash.
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# This section starts at the 16M boundary in SPI flash.
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# MTL does not support a region crossing this boundary,
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# MTL does not support a region crossing this boundary,
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@ -22,11 +17,6 @@ FLASH 32M {
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VBLOCK_B 8K
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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RW_FWID_B 64
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#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
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ME_RW_B(CBFS) 4500K
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#else
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ME_RW_B(CBFS) 4400K
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#endif
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}
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}
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RW_MISC 1M {
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RW_MISC 1M {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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@ -8,11 +8,6 @@ FLASH 32M {
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VBLOCK_A 8K
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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RW_FWID_A 64
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#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
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ME_RW_A(CBFS) 4500K
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#else
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ME_RW_A(CBFS) 4400K
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#endif
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}
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}
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# This section starts at the 16M boundary in SPI flash.
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# This section starts at the 16M boundary in SPI flash.
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# MTL does not support a region crossing this boundary,
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# MTL does not support a region crossing this boundary,
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@ -22,11 +17,6 @@ FLASH 32M {
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VBLOCK_B 8K
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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RW_FWID_B 64
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#if CONFIG_BOARD_GOOGLE_MODEL_REX_EC_ISH
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ME_RW_B(CBFS) 4500K
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#else
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ME_RW_B(CBFS) 4400K
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#endif
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}
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}
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RW_MISC 1M {
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RW_MISC 1M {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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