soc/intel/apollolake: Use CPU common library code
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I529c67cf20253cf819d1c13849300788104b083c Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -55,6 +55,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_ACPI
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_ITSS
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select SOC_INTEL_COMMON_BLOCK_I2C
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@ -18,7 +18,6 @@ bootblock-y += lpc_lib.c
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bootblock-y += mmap_boot.c
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bootblock-y += pmutil.c
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bootblock-y += spi.c
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bootblock-y += tsc_freq.c
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bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
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@ -32,7 +31,6 @@ romstage-y += lpc_lib.c
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romstage-y += memmap.c
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romstage-y += meminit.c
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romstage-y += mmap_boot.c
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romstage-y += tsc_freq.c
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romstage-y += pmutil.c
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romstage-y += reset.c
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romstage-y += spi.c
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@ -42,7 +40,6 @@ smm-y += pmutil.c
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smm-y += gpio.c
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smm-y += smihandler.c
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smm-y += spi.c
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smm-y += tsc_freq.c
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smm-y += uart_early.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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@ -65,7 +62,6 @@ ramstage-y += uart.c
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ramstage-y += nhlt.c
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ramstage-y += systemagent.c
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ramstage-y += spi.c
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ramstage-y += tsc_freq.c
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ramstage-y += pmutil.c
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ramstage-y += pmc.c
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ramstage-y += reset.c
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@ -79,7 +75,6 @@ postcar-y += memmap.c
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postcar-y += mmap_boot.c
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postcar-y += spi.c
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postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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postcar-y += tsc_freq.c
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postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
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@ -89,7 +84,6 @@ verstage-y += heci.c
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verstage-y += memmap.c
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verstage-y += mmap_boot.c
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verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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verstage-y += tsc_freq.c
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verstage-y += pmutil.c
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verstage-y += reset.c
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verstage-y += spi.c
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@ -17,6 +17,7 @@
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#include <arch/cpu.h>
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#include <bootblock_common.h>
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#include <device/pci.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/rtc.h>
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@ -17,8 +17,9 @@
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#include <arch/cpu.h>
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#include <assert.h>
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#include <cpu/x86/msr.h>
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#include <intelblocks/msr.h>
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#include <program_loading.h>
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#include <soc/cpu.h>
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/*
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* This file supports the necessary hoops one needs to jump through since
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@ -22,16 +22,18 @@
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#include <console/console.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/msr.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/itss.h>
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#include <romstage_handoff.h>
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#include <soc/iomap.h>
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#include <soc/itss.h>
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#include <soc/cpu.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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@ -547,7 +549,7 @@ struct chip_operations soc_intel_apollolake_ops = {
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static void drop_privilege_all(void)
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{
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/* Drop privilege level on all the CPUs */
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if (mp_run_on_all_cpus(&enable_untrusted_mode, 1000) < 0)
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if (mp_run_on_all_cpus(&cpu_enable_untrusted_mode, 1000) < 0)
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printk(BIOS_ERR, "failed to enable untrusted mode\n");
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}
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@ -28,7 +28,9 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/msr.h>
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#include <reg_script.h>
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#include <romstage_handoff.h>
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#include <soc/cpu.h>
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@ -58,13 +60,6 @@ static const struct reg_script core_msr_script[] = {
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REG_SCRIPT_END
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};
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void enable_untrusted_mode(void)
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{
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msr_t msr = rdmsr(MSR_POWER_MISC);
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msr.lo |= ENABLE_IA_UNTRUSTED;
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wrmsr(MSR_POWER_MISC, msr);
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}
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static void soc_core_init(device_t cpu)
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{
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/* Set core MSRs */
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@ -18,23 +18,10 @@
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#ifndef _SOC_APOLLOLAKE_CPU_H_
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#define _SOC_APOLLOLAKE_CPU_H_
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#include <intelblocks/msr.h>
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#ifndef __ASSEMBLER__
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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void set_max_freq(void);
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void enable_untrusted_mode(void);
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#endif
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#define CPUID_APOLLOLAKE_A0 0x506c8
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#define CPUID_APOLLOLAKE_B0 0x506c9
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/* Common Timer Copy (CTC) frequency - 19.2MHz. */
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#define CTC_FREQ 19200000
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/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */
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#define APL_BURST_MODE_DISABLE 0x40
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#endif /* _SOC_APOLLOLAKE_CPU_H_ */
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@ -21,6 +21,7 @@
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#include <arch/cpu.h>
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#include <fsp/api.h>
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void set_max_freq(void);
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void mainboard_memory_init_params(FSPM_UPD *mupd);
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void mainboard_save_dimm_info(void);
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@ -25,6 +25,7 @@
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#include <rules.h>
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#include <device/pci_def.h>
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#include <halt.h>
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#include <intelblocks/msr.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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#include <soc/pci_devs.h>
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@ -31,6 +31,7 @@
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#include <fsp/api.h>
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#include <fsp/memmap.h>
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#include <fsp/util.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/systemagent.h>
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#include <reset.h>
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#include <soc/cpu.h>
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@ -188,6 +189,27 @@ static bool punit_init(void)
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return true;
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}
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void set_max_freq(void)
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{
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if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) {
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/* Burst Mode has been factory configured as disabled
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* and is not available in this physical processor
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* package.
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*/
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printk(BIOS_DEBUG, "Burst Mode is factory disabled\n");
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return;
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}
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/* Enable burst mode */
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cpu_enable_burst_mode();
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/* Enable speed step. */
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cpu_enable_eist();
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/* Set P-State ratio */
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cpu_set_p_state_to_turbo_ratio();
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}
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asmlinkage void car_stage_entry(void)
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{
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struct postcar_frame pcf;
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@ -1,62 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/intel/speedstep.h>
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#include <cpu/intel/turbo.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/tsc.h>
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#include <soc/cpu.h>
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#include <console/console.h>
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#include <delay.h>
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#include "chip.h"
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void set_max_freq(void)
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{
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msr_t msr, msr_rd;
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unsigned int eax;
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eax = cpuid_eax(CPUID_LEAF_PM);
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msr = rdmsr(MSR_IA32_MISC_ENABLES);
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eax &= 0x2;
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if ((!eax) && ((msr.hi & APL_BURST_MODE_DISABLE) == 0)) {
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/* Burst Mode has been factory configured as disabled
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* and is not available in this physical processor
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* package.
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*/
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printk(BIOS_DEBUG, "Burst Mode is factory disabled\n");
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return;
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}
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/* Enable burst mode */
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msr.hi &= ~APL_BURST_MODE_DISABLE;
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wrmsr(MSR_IA32_MISC_ENABLES, msr);
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/* Enable speed step. */
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msr = rdmsr(MSR_IA32_MISC_ENABLES);
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msr.lo |= 1 << 16;
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wrmsr(MSR_IA32_MISC_ENABLES, msr);
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/* Set P-State ratio */
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msr = rdmsr(IA32_PERF_CTL);
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msr.lo &= ~0xff00;
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/* Read the frequency limit ratio and set it properly in PERF_CTL */
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msr_rd = rdmsr(FREQ_LIMIT_RATIO);
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msr.lo |= (msr_rd.lo & 0xff) << 8;
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wrmsr(IA32_PERF_CTL, msr);
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}
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