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soc/apl: add options to override USB port config 

Allows to override the PortUsb20Enable and PortUsb30Enable FSP options
(which are set to 1 by default) to enable/disable USB ports if the
usb_config_override flag is set to "1". Therefore, these changes will
not affect other boards with an Apollo Lake processor.

Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Maxim Polyakov 2020-02-16 11:51:57 +03:00 committed by Patrick Georgi
parent 44fc40e091
commit 6704049fc9
3 changed files with 47 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
src/soc/intel/apollolake/chip.c
View File

@ -558,11 +558,18 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig)
static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
*cfg, FSP_S_CONFIG *silconfig)
{
#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these
fields in FspsUpd.h yet */
#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these fields in FspsUpd.h yet */
uint8_t port;
for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
if (cfg->usb_config_override) {
if (!cfg->usb2_port[port].enable)
continue;
silconfig->PortUsb20Enable[port] = 1;
silconfig->PortUs20bOverCurrentPin[port] = cfg->usb2_port[port].oc_pin;
}
if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0)
silconfig->PortUsb20PerPortTxPeHalf[port] =
cfg->usb2eye[port].Usb20PerPortTxPeHalf;
@ -591,6 +598,16 @@ static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
silconfig->PortUsb20HsNpreDrvSel[port] =
cfg->usb2eye[port].Usb20HsNpreDrvSel;
}
if (cfg->usb_config_override) {
for (port = 0; port < APOLLOLAKE_USB3_PORT_MAX; port++) {
if (!cfg->usb3_port[port].enable)
continue;
silconfig->PortUsb30Enable[port] = 1;
silconfig->PortUs30bOverCurrentPin[port] = cfg->usb3_port[port].oc_pin;
}
}
#endif
}

5
src/soc/intel/apollolake/chip.h
View File

@ -136,6 +136,11 @@ struct soc_intel_apollolake_config {
/* USB2 eye diagram settings per port */
struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX];
/* Override USB port configuration */
uint8_t usb_config_override;
struct usb_port_config usb2_port[APOLLOLAKE_USB2_PORT_MAX];
struct usb_port_config usb3_port[APOLLOLAKE_USB3_PORT_MAX];
/* GPIO SD card detect pin */
unsigned int sdcard_cd_gpio;

23
src/soc/intel/apollolake/include/soc/usb.h
View File

@ -21,6 +21,12 @@
#include <stdint.h>
#define APOLLOLAKE_USB2_PORT_MAX 8
#define APOLLOLAKE_USB3_PORT_MAX 6
struct usb_port_config {
uint8_t enable;
uint8_t oc_pin;
};
struct usb2_eye_per_port {
uint8_t Usb20PerPortTxPeHalf;
@ -33,4 +39,21 @@ struct usb2_eye_per_port {
uint8_t Usb20OverrideEn;
};
/* USB overcurrent pins definition */
enum {
OC0 = 0,
OC1 = 1,
OC_SKIP = 2,
};
#define PORT_EN(pin) { \
.enable = 1, \
.oc_pin = (pin), \
}
#define PORT_DIS { \
.enable = 0, \
.oc_pin = OC_SKIP, \
}
#endif /* _SOC_APOLLOLAKE_USB_H_ */