just a few changes before we hit the big fun.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
1ddc8eaddb
commit
6707a45eb1
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@ -1,108 +1,125 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include <arch/smp/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/via/vt8601/raminit.h"
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#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c"
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#include "northbridge/intel/i855pm/raminit.h"
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#if 1
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#include "cpu/p6/apic_timer.c"
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#include "lib/delay.c"
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#endif
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#include "cpu/p6/boot_cpu.c"
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#include "northbridge/intel/i855pm/debug.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "cpu/p6/earlymtrr.c"
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#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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/*
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*/
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void udelay(int usecs)
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static void hard_reset(void)
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{
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int i;
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for(i = 0; i < usecs; i++)
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outb(i&0xff, 0x80);
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outb(0x0e, 0x0cf9);
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}
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "debug.c"
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#include "southbridge/via/vt8231/vt8231_early_serial.c"
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static void enable_mainboard_devices(void)
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static void memreset_setup(void)
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{
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device_t dev;
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/* dev 0 for southbridge */
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dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
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if (dev == PCI_DEV_INVALID) {
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die("Southbridge not found!!!\n");
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}
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pci_write_config8(dev, 0x50, 7);
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pci_write_config8(dev, 0x51, 0xff);
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#if 0
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// This early setup switches IDE into compatibility mode before PCI gets
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// // a chance to assign I/Os
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// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
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// // movb $0x09, %dl
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// movb $0x00, %dl
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// PCI_WRITE_CONFIG_BYTE
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//
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#endif
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/* we do this here as in V2, we can not yet do raw operations
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* to pci!
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*/
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dev += 0x100; /* ICKY */
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pci_write_config8(dev, 0x42, 0);
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}
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static void enable_shadow_ram(void)
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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device_t dev = 0; /* no need to look up 0:0.0 */
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unsigned char shadowreg;
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/* dev 0 for southbridge */
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shadowreg = pci_read_config8(dev, 0x63);
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/* 0xf0000-0xfffff */
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shadowreg |= 0x30;
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pci_write_config8(dev, 0x63, shadowreg);
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/intel/i855pm/raminit.c"
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#include "northbridge/intel/i855pm/reset_test.c"
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#include "sdram/generic_sdram.c"
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static void main(void)
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{
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unsigned long x;
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/* init_timer();*/
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outb(5, 0x80);
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enable_vt8231_serial();
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uart_init();
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console_init();
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enable_mainboard_devices();
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enable_smbus();
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enable_shadow_ram();
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/* Check all of memory */
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#if 0
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ram_check(0x00000000, msr.lo);
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#endif
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#if 0
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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#if TOTAL_CPUS > 1
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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#endif
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static const struct mem_controller memctrl[] = {
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{
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.d0 = PCI_DEV(0, 0, 0),
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.channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
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},
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};
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int i;
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for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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#if 1
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enable_lapic();
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init_timer();
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#endif
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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#if 1
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print_pci_devices();
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#endif
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if(!bios_reset_detected()) {
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enable_smbus();
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#if 1
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// dump_spd_registers(&memctrl[0]);
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dump_smbus_registers();
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#endif
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memreset_setup();
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sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
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}
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#if 0
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else {
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/* clear memory 1meg */
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__asm__ volatile(
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"1: \n\t"
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"movl %0, %%fs:(%1)\n\t"
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"addl $4,%1\n\t"
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"subl $4,%2\n\t"
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"jnz 1b\n\t"
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:
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: "a" (0), "D" (0), "c" (1024*1024)
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);
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}
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#endif
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early_mtrr_init();
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#if 1
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dump_pci_devices();
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#endif
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#if 1
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dump_pci_device(PCI_DEV(0, 0, 0));
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#endif
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/*
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#if 0
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ram_check(0x00000000, msr.lo+(msr.hi<<32));
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#else
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#if 0
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// Check 16MB of memory @ 0
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ram_check(0x00000000, 0x01000000);
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#else
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// Check 16MB of memory @ 2GB
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ram_check(0x80000000, 0x81000000);
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#endif
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#endif
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*/
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}
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@ -1980,7 +1980,15 @@ static void mem_err {
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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{
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int i;
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uint32_t mchtst;
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/* 1 & 2 Power up and start clocks */
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/* arg! the parts are memory mapped! For now, just grab address 0xc0000000 as the base, since I want to use
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* constants, not variables, for this.
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*/
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mchtst = pci_read_config32(ctrl->d0, 0xf4);
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mchtst |= (1 << 22);
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pci_write_config32(ctrl->d0, 0xf4, mchtst);
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#if DEBUG_RAM_CONFIG
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print_debug(ram_enable_1);
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print_debug(ram_enable_2);
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@ -1,6 +1,7 @@
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#ifndef RAMINIT_H
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#define RAMINIT_H
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/* I think the 855 is only four sockets -- RGM */
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#define DIMM_SOCKETS 4
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struct mem_controller {
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device_t d0;
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@ -1,4 +1,5 @@
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/* Convert to C by yhlu */
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/* converted to 855 by RGM */
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#define MCH_DRC 0x70
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#define DRC_DONE (1 << 29)
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/* If I have already booted once skip a bunch of initialization */
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