google/cyan: Remove support for pre-EVT board
Cleaning up code to remove support for pre-EVT rev of cyan board.
Analogous to what was done for intel/strago in commit 103f00d.
Change-Id: I29b32da8064e0743cc9c5df02ce7d3441459ee8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Matt DeVillier
Martin Roth
parent
3d4f04f6b1
commit
6712b231bc
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@ -22,7 +22,6 @@ romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
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ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c
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ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c
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ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio_pre_evt.c
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ramstage-y += irqroute.c
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ramstage-y += ramstage.c
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ramstage-y += w25q64.c
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@ -38,21 +38,6 @@ Scope (\_SB.PCI0.I2C1)
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Method(_CRS, 0x0, NotSerialized)
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{
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Name(BUF0,ResourceTemplate ()
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{
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I2CSerialBus(
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0x10, /* SlaveAddress */
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ControllerInitiated, /* SlaveMode */
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400000, /* ConnectionSpeed */
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AddressingMode7Bit, /* AddressingMode */
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"\\_SB.PCI0.I2C1", /* ResourceSource */
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)
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Interrupt (ResourceConsumer, Edge, ActiveLow)
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{
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BOARD_PRE_EVT_TOUCH_IRQ
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}
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} )
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Name(BUF1,ResourceTemplate ()
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{
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I2CSerialBus(
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0x10, /* SlaveAddress */
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@ -67,11 +52,7 @@ Scope (\_SB.PCI0.I2C1)
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}
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} )
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If (LEqual (\BDID, BOARD_EVT)) {
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Return (BUF1)
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} Else {
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Return (BUF0)
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}
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Return (BUF0)
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}
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Method (_STA)
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@ -17,7 +17,6 @@
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#include "irqroute.h"
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#include <soc/gpio.h>
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#include <stdlib.h>
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#include "gpio.h"
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/* South East Community */
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static const struct soc_gpio_map gpse_gpio_map[] = {
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@ -249,7 +248,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
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static struct soc_gpio_config gpio_config = {
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/* BSW */
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/* gpio configuration for EVT board */
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.north = gpn_gpio_map,
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.southeast = gpse_gpio_map,
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.southwest = gpsw_gpio_map,
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@ -258,11 +256,5 @@ static struct soc_gpio_config gpio_config = {
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struct soc_gpio_config *mainboard_get_gpios(void)
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{
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return get_override_gpios(&gpio_config);
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}
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__attribute__((weak)) struct soc_gpio_config *get_override_gpios(
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struct soc_gpio_config *config)
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{
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return config;
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return &gpio_config;
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}
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@ -1,20 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _BOARD_GPIO_H_
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#define _BOARD_GPIO_H_
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struct soc_gpio_config *get_override_gpios(struct soc_gpio_config *config);
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#endif
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@ -1,267 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright(C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "irqroute.h"
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#include <soc/gpio.h>
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#include <stdlib.h>
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#include <boardid.h>
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#include "onboard.h"
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#include "gpio.h"
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/* South East Community */
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static const struct soc_gpio_map gpse_gpio_map[] = {
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Native_M1,/* MF_PLT_CLK0 */
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GPIO_NC, /* 01 PWM1 */
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GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */
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GPIO_NC, /* 03 MF_PLT_CLK4 */
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GPIO_NC, /* 04 MF_PLT_CLK3 */
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GPIO_NC, /* PWM0 05 */
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GPIO_NC, /* 06 MF_PLT_CLK5 */
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GPIO_NC, /* 07 MF_PLT_CLK2 */
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GPIO_NC, /* 15 SDMMC2_D3_CD_B */
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Native_M1, /* 16 SDMMC1_CLK */
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NATIVE_PU20K(1), /* 17 SDMMC1_D0 */
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GPIO_NC, /* 18 SDMMC2_D1 */
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GPIO_NC, /* 19 SDMMC2_CLK */
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NATIVE_PU20K(1),/* 20 SDMMC1_D2 */
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GPIO_NC, /* 21 SDMMC2_D2 */
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GPIO_NC, /* 22 SDMMC2_CMD */
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NATIVE_PU20K(1), /* 23 SDMMC1_CMD */
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NATIVE_PU20K(1), /* 24 SDMMC1_D1 */
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GPIO_NC, /* 25 SDMMC2_D0 */
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NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */
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NATIVE_PU20K(1), /* 30 SDMMC3_D1 */
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Native_M1, /* 31 SDMMC3_CLK */
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NATIVE_PU20K(1), /* 32 SDMMC3_D3 */
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NATIVE_PU20K(1), /* 33 SDMMC3_D2 */
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NATIVE_PU20K(1), /* 34 SDMMC3_CMD */
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NATIVE_PU20K(1), /* 35 SDMMC3_D0 */
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NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */
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Native_M1, /* 46 LPC_CLKRUNB */
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NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */
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Native_M1, /* 48 LPC_FRAMEB */
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Native_M1, /* 49 MF_LPC_CLKOUT1 */
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NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */
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Native_M1, /* 51 MF_LPC_CLKOUT0 */
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NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */
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Native_M1,/* SPI1_MISO */
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Native_M1, /* 61 SPI1_CS0_B */
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Native_M1, /* SPI1_CLK */
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NATIVE_PU20K(1), /* 63 MMC1_D6 */
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Native_M1, /* 62 SPI1_MOSI */
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NATIVE_PU20K(1), /* 65 MMC1_D5 */
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GPIO_NC, /* SPI1_CS1_B 66 */
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NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */
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NATIVE_PU20K(1), /* 68 MMC1_D7 */
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GPIO_NC, /* 69 MMC1_RCLK */
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Native_M1, /* 75 GPO USB_OC1_B */
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Native_M1, /* 76 PMU_RESETBUTTON_B */
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GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
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/* GPIO_ALERT 77 */
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Native_M1, /* 78 SDMMC3_PWR_EN_B */
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GPIO_NC, /* 79 GPI ILB_SERIRQ */
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Native_M1, /* 80 USB_OC0_B */
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NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */
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GPIO_NC, /* 82 spkr asummed gpio number */
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Native_M1, /* 83 SUSPWRDNACK */
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SPARE_PIN,/* 84 spare pin */
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Native_M1, /* 85 SDMMC3_1P8_EN */
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GPIO_END
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};
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/* South West Community */
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static const struct soc_gpio_map gpsw_gpio_map[] = {
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GPIO_NC, /* 00 FST_SPI_D2 */
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Native_M1, /* 01 FST_SPI_D0 */
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Native_M1, /* 02 FST_SPI_CLK */
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GPIO_NC, /* 03 FST_SPI_D3 */
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GPIO_NC, /* GPO FST_SPI_CS1_B */
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Native_M1, /* 05 FST_SPI_D1 */
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Native_M1, /* 06 FST_SPI_CS0_B */
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GPIO_NC, /* 07 FST_SPI_CS2_B */
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GPIO_NC, /* 15 UART1_RTS_B */
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Native_M2, /* 16 UART1_RXD */
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GPIO_NC, /* 17 UART2_RXD */
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GPIO_NC, /* 18 UART1_CTS_B */
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GPIO_NC, /* 19 UART2_RTS_B */
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Native_M2, /* 20 UART1_TXD */
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GPIO_NC, /* 21 UART2_TXD */
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GPIO_NC, /* 22 UART2_CTS_B */
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GPIO_NC, /* 30 MF_HDA_CLK */
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GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */
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GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */
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GPIO_NC, /* 33 MF_HDA_SDO */
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GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA),
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/* 34 MF_HDA_DOCKRSTB */
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GPIO_NC, /* 35 MF_HDA_SYNC */
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GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */
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GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
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/* 37 MF_HDA_DOCKENB */
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NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
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GPIO_NC, /* 46 I2C4_SDA */
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NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */
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NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */
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GPIO_NC, /* 49 I2C_NFC_SDA */
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GPIO_NC, /* 50 I2C4_SCL */
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NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */
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GPIO_NC, /* 52 I2C_NFC_SCL */
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NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */
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NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */
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NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */
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NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */
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GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/
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NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */
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NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */
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GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */
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GPIO_OUT_HIGH, /* 75 SATA_GP0 */
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GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
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/* 76 GPI SATA_GP1 */
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Native_M1, /* 77 SATA_LEDN */
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GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */
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Native_M1, /* 79 MF_SMB_ALERTB */
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GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
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Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
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Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
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/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
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Native_M1, /* 90 PCIE_CLKREQ0B */
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GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */
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Native_M1, /* 92 GP_SSP_2_CLK */
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NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */
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Native_M1, /* 94 GP_SSP_2_RXD */
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GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),
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/* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */
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Native_M1, /* 96 GP_SSP_2_FS */
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NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */
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GPIO_END
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};
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/* North Community */
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static const struct soc_gpio_map gpn_gpio_map[] = {
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Native_M5, /* 00 GPIO_DFX0 */
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Native_M5, /* 01 GPIO_DFX3 */
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Native_M1, /* 02 GPIO_DFX7 */
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Native_M5, /* 03 GPIO_DFX1 */
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Native_M1, /* 04 GPIO_DFX5 */
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Native_M1, /* 05 GPIO_DFX4 */
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GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA),
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/* 06 GPIO_DFX8 */
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Native_M5, /* 07 GPIO_DFX2 */
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Native_M8, /* 08 GPIO_DFX6 */
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GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
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UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
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GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
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GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
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/* 17 GPIO_SUS3 */
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GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
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/* 18 GPIO_SUS7 */
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GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */
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GPIO_NC, /* 20 GPIO_SUS5 */
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GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA),
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/* 21 SEC_GPIO_SUS11 */
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GPIO_NC, /* 22 GPIO_SUS4 */
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GPIO_NC,
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/* 23 SEC_GPIO_SUS8 */
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Native_M6, /* 24 GPIO_SUS2 */
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GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */
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Native_M1, /* 26 CX_PREQ_B */
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GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */
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Native_M1, /* 30 TRST_B */
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Native_M1, /* 31 TCK */
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GPIO_SKIP, /* 32 PROCHOT_B */
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GPIO_SKIP, /* 33 SVID0_DATA */
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Native_M1, /* 34 TMS */
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GPIO_NC, /* 35 CX_PRDY_B_2 */
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GPIO_NC, /* 36 TDO_2 */
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Native_M1, /* 37 CX_PRDY_B */
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GPIO_SKIP, /* 38 SVID0_ALERT_B */
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Native_M1, /* 39 TDO */
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GPIO_SKIP, /* 40 SVID0_CLK */
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Native_M1, /* 41 TDI */
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Native_M2, /* 45 GP_CAMERASB05 */
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Native_M2, /* 46 GP_CAMERASB02 */
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Native_M2, /* 47 GP_CAMERASB08 */
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Native_M2, /* 48 GP_CAMERASB00 */
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Native_M2, /* 49 GP_CAMERASBO6 */
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GPIO_NC, /* 50 GP_CAMERASB10 */
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Native_M2, /* 51 GP_CAMERASB03 */
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GPIO_NC, /* 52 GP_CAMERASB09 */
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Native_M2, /* 53 GP_CAMERASB01 */
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Native_M2, /* 54 GP_CAMERASB07 */
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GPIO_NC, /* 55 GP_CAMERASB11 */
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Native_M2, /* 56 GP_CAMERASB04 */
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GPIO_NC, /* 60 PANEL0_BKLTEN */
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GPIO_NC, /* 61 HV_DDI0_HPD */
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NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */
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Native_M1, /* 63 PANEL1_BKLTCTL */
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NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */
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GPIO_NC, /* 65 PANEL0_BKLTCTL */
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GPIO_NC, /* 66 HV_DDI0_DDC_SDA */
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NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */
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NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */
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Native_M1, /* 69 PANEL1_VDDEN */
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Native_M1, /* 70 PANEL1_BKLTEN */
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GPIO_NC, /* 71 HV_DDI0_DDC_SCL */
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GPIO_NC, /* 72 PANEL0_VDDEN */
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GPIO_END
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};
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/* East Community */
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static const struct soc_gpio_map gpe_gpio_map[] = {
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Native_M1, /* 00 PMU_SLP_S3_B */
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GPIO_NC, /* 01 PMU_BATLOW_B */
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Native_M1, /* 02 SUS_STAT_B */
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Native_M1, /* 03 PMU_SLP_S0IX_B */
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Native_M1, /* 04 PMU_AC_PRESENT */
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Native_M1, /* 05 PMU_PLTRST_B */
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Native_M1, /* 06 PMU_SUSCLK */
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GPIO_NC, /* 07 PMU_SLP_LAN_B */
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Native_M1, /* 08 PMU_PWRBTN_B */
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Native_M1, /* 09 PMU_SLP_S4_B */
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NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */
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GPIO_NC, /* 11 PMU_WAKE_LAN_B */
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GPIO_NC, /* 15 MF_GPIO_3 */
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GPIO_NC, /* 16 MF_GPIO_7 */
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GPIO_NC, /* 17 MF_I2C1_SCL */
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GPIO_NC, /* 18 MF_GPIO_1 */
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GPIO_NC, /* 19 MF_GPIO_5 */
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GPIO_NC, /* 20 MF_GPIO_9 */
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GPIO_NC, /* 21 MF_GPIO_0 */
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GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */
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GPIO_NC, /* 23 MF_GPIO_8 */
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GPIO_NC, /* 24 MF_GPIO_2 */
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GPIO_NC, /* 25 MF_GPIO_6 */
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GPIO_NC, /* 26 MF_I2C1_SDA */
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GPIO_END
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};
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static struct soc_gpio_config gpio_config = {
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/* BSW */
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/* gpio configuration for pre-evt board */
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.north = gpn_gpio_map,
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.southeast = gpse_gpio_map,
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.southwest = gpsw_gpio_map,
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.east = gpe_gpio_map
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};
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struct soc_gpio_config *get_override_gpios(struct soc_gpio_config *config)
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{
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if (board_id() == BOARD_PRE_EVT)
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return &gpio_config;
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return config;
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}
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@ -31,7 +31,6 @@
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*/
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||||
|
||||
#define BOARD_TOUCH_IRQ 184
|
||||
#define BOARD_PRE_EVT_TOUCH_IRQ 156
|
||||
|
||||
/* KBD: Gpio index in N bank */
|
||||
#define BOARD_I8042_GPIO_INDEX 17
|
||||
|
|
@ -39,10 +38,8 @@
|
|||
#define BOARD_SCI_GPIO_INDEX 15
|
||||
/* Trackpad: Gpio index in N bank */
|
||||
#define BOARD_TRACKPAD_GPIO_INDEX 18
|
||||
/* Touch: Gpio index in SW bank */
|
||||
#define BOARD_TOUCH_GPIO_INDEX 76
|
||||
/* EVT Touch: Gpio index in N bank */
|
||||
#define BOARD_EVT_TOUCH_GPIO_INDEX 19
|
||||
/* Touch: Gpio index in N bank */
|
||||
#define BOARD_TOUCH_GPIO_INDEX 19
|
||||
/* TI Audio: Gpio index in SW bank */
|
||||
#define BOARD_JACK_TI_GPIO_INDEX 34
|
||||
/* MAXIM Audio: Gpio index in SE bank */
|
||||
|
|
@ -72,8 +69,6 @@
|
|||
#define TI_SWITCH_DDN "TI SWITCH "
|
||||
#define TI_SWITCH_I2C_ADDR 0x3B
|
||||
|
||||
#define BOARD_PRE_EVT 0x01
|
||||
#define BOARD_EVT 0x02
|
||||
#endif
|
||||
|
||||
#define DPTF_CPU_PASSIVE 88
|
||||
|
|
|
|||
|
|
@ -19,6 +19,4 @@
|
|||
|
||||
void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
|
||||
{
|
||||
if (board_id() == BOARD_PRE_EVT)
|
||||
params->ChvSvidConfig = SVID_CONFIG3;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -152,13 +152,6 @@ void mainboard_smi_sleep(uint8_t slp_typ)
|
|||
/* Clear pending events that may trigger immediate wake */
|
||||
while (google_chromeec_get_event() != 0)
|
||||
;
|
||||
|
||||
if (smm_get_gnvs()->bdid == BOARD_PRE_EVT) {
|
||||
/* Set LPC lines to low power in S3/S5. */
|
||||
if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))
|
||||
lpc_set_low_power();
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue