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southbridge/intel/i82801dx: use common Intel ACPI hardware definitions 

Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I29918fe70b5e511785ed920d8953de3281694be2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15678
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2016-07-13 23:24:36 -05:00
parent 78c6843a2b
commit 671909b891
3 changed files with 9 additions and 8 deletions
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1
src/southbridge/intel/i82801dx/Kconfig
View File

@ -16,6 +16,7 @@
config SOUTHBRIDGE_INTEL_I82801DX config SOUTHBRIDGE_INTEL_I82801DX
bool bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON
select IOAPIC select IOAPIC
select HAVE_HARD_RESET select HAVE_HARD_RESET

4
src/southbridge/intel/i82801dx/i82801dx.h
View File

@ -27,6 +27,8 @@
#ifndef I82801DX_H #ifndef I82801DX_H
#define I82801DX_H #define I82801DX_H
#include <arch/acpi.h>
#if !defined(__ASSEMBLER__) #if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__) #if !defined(__PRE_RAM__)
#include "chip.h" #include "chip.h"
@ -147,8 +149,6 @@ int smbus_read_byte(unsigned device, unsigned address);
#define GBL_EN (1 << 5) #define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0) #define TMROF_EN (1 << 0)
#define PM1_CNT 0x04 #define PM1_CNT 0x04
#define SLP_EN (1 << 13)
#define SLP_TYP (7 << 10)
#define GBL_RLS (1 << 2) #define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1) #define BM_RLD (1 << 1)
#define SCI_EN (1 << 0) #define SCI_EN (1 << 0)

12
src/southbridge/intel/i82801dx/smihandler.c
View File

@ -286,21 +286,21 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
/* Figure out SLP_TYP */ /* Figure out SLP_TYP */
reg32 = inl(pmbase + PM1_CNT); reg32 = inl(pmbase + PM1_CNT);
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
slp_typ = (reg32 >> 10) & 7; slp_typ = acpi_sleep_from_pm1(reg32);
/* Next, do the deed. /* Next, do the deed.
*/ */
switch (slp_typ) { switch (slp_typ) {
case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
case 5: case ACPI_S3:
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
/* Invalidate the cache before going to S3 */ /* Invalidate the cache before going to S3 */
wbinvd(); wbinvd();
break; break;
case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
case 7: case ACPI_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
outl(0, pmbase + GPE0_EN); outl(0, pmbase + GPE0_EN);