diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 4c20d52dfd..bd7f4224ec 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -445,8 +445,7 @@ static int get_socket_type(void)
 
 unsigned int __weak smbios_memory_error_correction_type(struct memory_info *meminfo)
 {
-	return meminfo->ecc_capable ?
-		MEMORY_ARRAY_ECC_SINGLE_BIT : MEMORY_ARRAY_ECC_NONE;
+	return meminfo->ecc_type;
 }
 
 unsigned int __weak smbios_processor_external_clock(void)
diff --git a/src/include/memory_info.h b/src/include/memory_info.h
index 1ba73291a8..fed5bbe265 100644
--- a/src/include/memory_info.h
+++ b/src/include/memory_info.h
@@ -96,8 +96,11 @@ struct dimm_info {
 } __packed;
 
 struct memory_info {
-	/* controller specific */
-	bool ecc_capable;
+	/*
+	 * SMBIOS error correction type.
+	 * See the smbios.h smbios_memory_array_ecc enum.
+	 */
+	uint8_t ecc_type;
 	/* Maximum capacity the DRAM controller/mainboard supports */
 	uint32_t max_capacity_mib;
 	/* Maximum number of DIMMs the DRAM controller/mainboard supports */
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 96e6a2aeff..58ac8a05a3 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -167,9 +167,9 @@ void sdram_initialize(struct pei_data *pei_data)
 	report_memory_config();
 }
 
-static bool nb_supports_ecc(const uint32_t capid0_a)
+static uint8_t nb_get_ecc_type(const uint32_t capid0_a)
 {
-	return !(capid0_a & CAPID_ECCDIS);
+	return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
 }
 
 static uint16_t nb_slots_per_channel(const uint32_t capid0_a)
@@ -256,7 +256,7 @@ void setup_sdram_meminfo(struct pei_data *pei_data)
 
 	const uint16_t channels = nb_number_of_channels(capid0_a);
 
-	mem_info->ecc_capable = nb_supports_ecc(capid0_a);
+	mem_info->ecc_type = nb_get_ecc_type(capid0_a);
 	mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a);
 	mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a);
 }
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 0dcd952595..47cd7dee50 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -53,9 +53,9 @@ static void disable_channel(ramctr_timing *ctrl, int channel)
 	memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0]));
 }
 
-static bool nb_supports_ecc(const uint32_t capid0_a)
+static uint8_t nb_get_ecc_type(const uint32_t capid0_a)
 {
-	return !(capid0_a & CAPID_ECCDIS);
+	return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
 }
 
 static uint16_t nb_slots_per_channel(const uint32_t capid0_a)
@@ -114,7 +114,7 @@ static void setup_sdram_meminfo(ramctr_timing *ctrl)
 
 	const uint16_t channels = nb_number_of_channels(capid0_a);
 
-	m->ecc_capable = nb_supports_ecc(capid0_a);
+	m->ecc_type = nb_get_ecc_type(capid0_a);
 	m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a);
 	m->number_of_devices = channels * nb_slots_per_channel(capid0_a);
 }
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index ec26fce5ba..7d42fe1641 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -48,9 +48,9 @@ __weak uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
 	return 32768;	/* 32 GiB per channel */
 }
 
-static bool sa_supports_ecc(const uint32_t capid0_a)
+static uint8_t sa_get_ecc_type(const uint32_t capid0_a)
 {
-	return !(capid0_a & CAPID_ECCDIS);
+	return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
 }
 
 static size_t sa_slots_per_channel(const uint32_t capid0_a)
@@ -73,7 +73,7 @@ static void sa_soc_systemagent_init(struct device *dev)
 
 	const uint32_t capid0_a = pci_read_config32(dev, CAPID0_A);
 
-	m->ecc_capable = sa_supports_ecc(capid0_a);
+	m->ecc_type = sa_get_ecc_type(capid0_a);
 	m->max_capacity_mib = soc_systemagent_max_chan_capacity_mib(CAPID_DDRSZ(capid0_a)) *
 			      sa_number_of_channels(capid0_a);
 	m->number_of_devices = sa_slots_per_channel(capid0_a) *