mb/google/dedede: Add waddledee variant
Add initial support for waddledee variant board. BUG=b:151576904 TEST=Build the mainboard and variant board. Change-Id: I20d41fbbb78c7fd2f964a97ffebbc9c3bbfb1c5c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -53,6 +53,7 @@ config MAINBOARD_PART_NUMBER
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string
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default "Dedede" if BOARD_GOOGLE_DEDEDE
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default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO
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default "Waddledee" if BOARD_GOOGLE_WADDLEDEE
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config MAX_CPUS
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int
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@ -74,5 +75,6 @@ config VARIANT_DIR
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string
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default "dedede" if BOARD_GOOGLE_DEDEDE
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default "waddledoo" if BOARD_GOOGLE_WADDLEDOO
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default "waddledee" if BOARD_GOOGLE_WADDLEDEE
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endif #BOARD_GOOGLE_BASEBOARD_DEDEDE
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@ -9,3 +9,9 @@ config BOARD_GOOGLE_WADDLEDOO
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select BOARD_GOOGLE_BASEBOARD_DEDEDE
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select BASEBOARD_DEDEDE_LAPTOP
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select BOARD_ROMSIZE_KB_32768
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config BOARD_GOOGLE_WADDLEDEE
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bool "Waddledee"
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select BOARD_GOOGLE_BASEBOARD_DEDEDE
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select BASEBOARD_DEDEDE_LAPTOP
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select BOARD_ROMSIZE_KB_32768
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@ -0,0 +1,11 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2020 The coreboot project Authors.
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##
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## SPDX-License-Identifier: GPL-2.0-or-later
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##
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SPD_SOURCES = empty #0b0000
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SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001
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SPD_SOURCES += samsung-K4U6E3S4AA-MGCL #0b0010
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@ -0,0 +1,14 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Authors.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef MAINBOARD_EC_H
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#define MAINBOARD_EC_H
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,14 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Authors.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <baseboard/gpio.h>
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#endif /* MAINBOARD_GPIO_H */
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@ -0,0 +1,40 @@
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chip soc/intel/tigerlake
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| I2C0 | Trackpad |
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#| I2C1 | Digitizer |
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#| I2C2 | Touchscreen |
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#| I2C3 | Camera |
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#| I2C4 | Audio |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on end
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end
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