mb/google/dedede: Add waddledee variant

Add initial support for waddledee variant board.

BUG=b:151576904
TEST=Build the mainboard and variant board.

Change-Id: I20d41fbbb78c7fd2f964a97ffebbc9c3bbfb1c5c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian 2020-03-15 23:25:37 -06:00 committed by Patrick Georgi
parent d3dab12244
commit 672f7d7b2d
6 changed files with 87 additions and 0 deletions

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@ -53,6 +53,7 @@ config MAINBOARD_PART_NUMBER
string
default "Dedede" if BOARD_GOOGLE_DEDEDE
default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO
default "Waddledee" if BOARD_GOOGLE_WADDLEDEE
config MAX_CPUS
int
@ -74,5 +75,6 @@ config VARIANT_DIR
string
default "dedede" if BOARD_GOOGLE_DEDEDE
default "waddledoo" if BOARD_GOOGLE_WADDLEDOO
default "waddledee" if BOARD_GOOGLE_WADDLEDEE
endif #BOARD_GOOGLE_BASEBOARD_DEDEDE

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@ -9,3 +9,9 @@ config BOARD_GOOGLE_WADDLEDOO
select BOARD_GOOGLE_BASEBOARD_DEDEDE
select BASEBOARD_DEDEDE_LAPTOP
select BOARD_ROMSIZE_KB_32768
config BOARD_GOOGLE_WADDLEDEE
bool "Waddledee"
select BOARD_GOOGLE_BASEBOARD_DEDEDE
select BASEBOARD_DEDEDE_LAPTOP
select BOARD_ROMSIZE_KB_32768

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@ -0,0 +1,11 @@
##
## This file is part of the coreboot project.
##
## Copyright 2020 The coreboot project Authors.
##
## SPDX-License-Identifier: GPL-2.0-or-later
##
SPD_SOURCES = empty #0b0000
SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001
SPD_SOURCES += samsung-K4U6E3S4AA-MGCL #0b0010

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@ -0,0 +1,14 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef MAINBOARD_EC_H
#define MAINBOARD_EC_H
#include <baseboard/ec.h>
#endif

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@ -0,0 +1,14 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <baseboard/gpio.h>
#endif /* MAINBOARD_GPIO_H */

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@ -0,0 +1,40 @@
chip soc/intel/tigerlake
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Trackpad |
#| I2C1 | Digitizer |
#| I2C2 | Touchscreen |
#| I2C3 | Camera |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on end
end