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vboot: Fix S3 resume with stage_cache 

In VBOOT_STARTS_IN_ROMSTAGE=y case, vboot_run_logic() did not
get called when postcar was loaded from TSEG stage cache on
ACPI S3 resume path. Resume failed as MP init attempts to
access microcode update from unverified FW_MAIN_A/B section.

In a similar fashion, for POSTCAR=n, loading ramstage from
TSEG stage cache would bypass the call to vboot_run_logic().

TEST=samsung/lumpy with VBOOT_STARTS_IN_ROMSTAGE=y is able
to complete S3 resume.

Change-Id: I77fe86d5fd89d22b5ef6f43e65a85a4ccd3259d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Kyösti Mälkki 2023-07-04 10:09:59 +03:00
parent 72d7181e4f
commit 6739a6a89f
2 changed files with 4 additions and 4 deletions
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4
src/arch/x86/postcar_loader.c
View File

@ -99,8 +99,6 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf)
.prog = prog,
};
vboot_run_logic();
if (rmodule_stage_load(&rsl))
die_with_post_code(POSTCODE_INVALID_ROM,
"Failed to load after CAR program.\n");
@ -162,6 +160,8 @@ static void run_postcar_phase(struct postcar_frame *pcf)
struct prog prog =
PROG_INIT(PROG_POSTCAR, CONFIG_CBFS_PREFIX "/postcar");
vboot_run_logic();
if (resume_from_stage_cache()) {
stage_cache_load_stage(STAGE_POSTCAR, &prog);
/* This is here to allow platforms to pass different stack

4
src/lib/prog_loaders.c
View File

@ -92,6 +92,8 @@ void __noreturn run_ramstage(void)
else
timestamp_add_now(TS_ROMSTAGE_END);
vboot_run_logic();
/*
* Only x86 systems using ramstage stage cache currently take the same
* firmware path on resume.
@ -99,8 +101,6 @@ void __noreturn run_ramstage(void)
if (ENV_X86 && resume_from_stage_cache())
run_ramstage_from_resume(&ramstage);
vboot_run_logic();
timestamp_add_now(TS_COPYRAM_START);
if (ENV_X86) {