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soc/amd/stoneyridge/acpi: Fix checkpatch errors 

Correct the checkpatch errors reported in the asl files and
make other stylistic modifications.

These changes were confirmed to cause no changes in a Gardenia
build.

BUG=chrome-os-partner:622407746

Change-Id: Id8b2620d161062c444e493325d83bb158705b76b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Marshall Dawson 2017-06-14 16:09:07 -06:00 committed by Martin Roth
parent a564811e71
commit 6744dfe7e0
6 changed files with 54 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/soc/amd/stoneyridge/acpi/fch.asl
View File

@ -72,38 +72,38 @@ Name(CRES, ResourceTemplate() {
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, /* address granularity */
0x0000, /* range minimum */
0x00FF, /* range maximum */
0x00ff, /* range maximum */
0x0000, /* translation */
0x0100, /* length */
,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
IO(Decode16, 0x0cf8, 0x0cf8, 1, 8)
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, /* address granularity */
0x0000, /* range minimum */
0x0CF7, /* range maximum */
0x0cf7, /* range maximum */
0x0000, /* translation */
0x0CF8 /* length */
0x0cf8 /* length */
)
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, /* address granularity */
0x03B0, /* range minimum */
0x03DF, /* range maximum */
0x03b0, /* range minimum */
0x03df, /* range maximum */
0x0000, /* translation */
0x0030 /* length */
)
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, /* address granularity */
0x0D00, /* range minimum */
0xFFFF, /* range maximum */
0x0d00, /* range minimum */
0xffff, /* range maximum */
0x0000, /* translation */
0xF300 /* length */
0xf300 /* length */
)
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
/* memory space for PCI BARs below 4GB */
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)

8
src/soc/amd/stoneyridge/acpi/lpc.asl
View File

@ -76,7 +76,7 @@ Device(LIBR) {
Name(_CRS, ResourceTemplate() {
IRQNoFlags(){2}
IO(Decode16,0x0020, 0x0020, 0, 2)
IO(Decode16,0x00A0, 0x00A0, 0, 2)
IO(Decode16,0x00a0, 0x00a0, 0, 2)
})
} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
@ -88,15 +88,15 @@ Device(LIBR) {
IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
IO(Decode16, 0x008f, 0x008f, 0x01, 0x01)
IO(Decode16, 0x00c0, 0x00c0, 0x10, 0x20)
}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
Device(COPR) {
Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
Name(_CRS, ResourceTemplate() {
IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
IO(Decode16, 0x00f0, 0x00f0, 0, 0x10)
IRQNoFlags(){13}
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */

2
src/soc/amd/stoneyridge/acpi/northbridge.asl
View File

@ -118,7 +118,7 @@ Device(AZHD) { /* 0:9.2 - HD Audio */
MMLA, 32,
offset (0x68),
MMHA, 32,
offset (0x6C),
offset (0x6c),
MMDT, 16,
}

44
src/soc/amd/stoneyridge/acpi/pci_int.asl
View File

@ -33,14 +33,14 @@
PT7D, 1,
PT8D, 1,
PT9D, 1,
Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
Offset(0x000a0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
SBIE, 1,
SBME, 1,
Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
Offset(0x000a0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
SBRI, 8,
Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
Offset(0x000a0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
SBB1, 32,
Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
Offset(0x000a0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
,14,
P92E, 1, /* Port92 decode enable */
}
@ -58,26 +58,26 @@
P0DD, 4,
, 4,
P0IS, 4,
Offset(0x12C), /* Port 0 Serial ATA control */
Offset(0x12c), /* Port 0 Serial ATA control */
P0DI, 4,
Offset(0x130), /* Port 0 Serial ATA error */
, 16,
P0PR, 1,
/* Port 1 */
offset(0x1A0), /* Port 1 Task file status */
offset(0x1a0), /* Port 1 Task file status */
P1ER, 1,
, 2,
P1DQ, 1,
, 3,
P1BY, 1,
Offset(0x1A8), /* Port 1 Serial ATA status */
Offset(0x1a8), /* Port 1 Serial ATA status */
P1DD, 4,
, 4,
P1IS, 4,
Offset(0x1AC), /* Port 1 Serial ATA control */
Offset(0x1ac), /* Port 1 Serial ATA control */
P1DI, 4,
Offset(0x1B0), /* Port 1 Serial ATA error */
Offset(0x1b0), /* Port 1 Serial ATA error */
, 16,
P1PR, 1,
@ -92,26 +92,26 @@
P2DD, 4,
, 4,
P2IS, 4,
Offset(0x22C), /* Port 2 Serial ATA control */
Offset(0x22c), /* Port 2 Serial ATA control */
P2DI, 4,
Offset(0x230), /* Port 2 Serial ATA error */
, 16,
P2PR, 1,
/* Port 3 */
Offset(0x2A0), /* Port 3 Task file status */
Offset(0x2a0), /* Port 3 Task file status */
P3ER, 1,
, 2,
P3DQ, 1,
, 3,
P3BY, 1,
Offset(0x2A8), /* Port 3 Serial ATA status */
Offset(0x2a8), /* Port 3 Serial ATA status */
P3DD, 4,
, 4,
P3IS, 4,
Offset(0x2AC), /* Port 3 Serial ATA control */
Offset(0x2aC), /* Port 3 Serial ATA control */
P3DI, 4,
Offset(0x2B0), /* Port 3 Serial ATA error */
Offset(0x2b0), /* Port 3 Serial ATA error */
, 16,
P3PR, 1,
}
@ -146,7 +146,7 @@
Method(_STA, 0) {
if (PIRA) {
Return(0x0B) /* sata is invisible */
Return(0x0b) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
}
@ -187,7 +187,7 @@
Method(_STA, 0) {
if (PIRB) {
Return(0x0B) /* sata is invisible */
Return(0x0b) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
}
@ -228,7 +228,7 @@
Method(_STA, 0) {
if (PIRC) {
Return(0x0B) /* sata is invisible */
Return(0x0b) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
}
@ -269,7 +269,7 @@
Method(_STA, 0) {
if (PIRD) {
Return(0x0B) /* sata is invisible */
Return(0x0b) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
}
@ -310,7 +310,7 @@
Method(_STA, 0) {
if (PIRE) {
Return(0x0B) /* sata is invisible */
Return(0x0b) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
}
@ -351,7 +351,7 @@
Method(_STA, 0) {
if (PIRF) {
Return(0x0B) /* sata is invisible */
Return(0x0b) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
}
@ -392,7 +392,7 @@
Method(_STA, 0) {
if (PIRG) {
Return(0x0B) /* sata is invisible */
Return(0x0b) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
}
@ -433,7 +433,7 @@
Method(_STA, 0) {
if (PIRH) {
Return(0x0B) /* sata is invisible */
Return(0x0b) /* sata is invisible */
} else {
Return(0x09) /* sata is disabled */
}

16
src/soc/amd/stoneyridge/acpi/pcie.asl
View File

@ -14,7 +14,7 @@
*/
/* PCI IRQ mapping registers, C00h-C01h. */
OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
Field(PRQM, ByteAcc, NoLock, Preserve) {
PRQI, 0x00000008,
PRQD, 0x00000008, /* Offset: 1h */
@ -31,7 +31,7 @@
}
/* PCI Error control register */
OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
OperationRegion(PERC, SystemIO, 0x00000c14, 0x00000001)
Field(PERC, ByteAcc, NoLock, Preserve) {
SENS, 0x00000001,
PENS, 0x00000001,
@ -40,7 +40,7 @@
}
/* Client Management index/data registers */
OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
OperationRegion(CMT, SystemIO, 0x00000c50, 0x00000002)
Field(CMT, ByteAcc, NoLock, Preserve) {
CMTI, 8,
/* Client Management Data register */
@ -52,7 +52,7 @@
}
/* GPM Port register */
OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
OperationRegion(GPT, SystemIO, 0x00000c52, 0x00000001)
Field(GPT, ByteAcc, NoLock, Preserve) {
GPB0,1,
GPB1,1,
@ -65,21 +65,21 @@
}
/* Flash ROM program enable register */
OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
OperationRegion(FRE, SystemIO, 0x00000c6F, 0x00000001)
Field(FRE, ByteAcc, NoLock, Preserve) {
, 0x00000006,
FLRE, 0x00000001,
}
/* PM2 index/data registers */
OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
OperationRegion(PM2R, SystemIO, 0x00000Cd0, 0x00000002)
Field(PM2R, ByteAcc, NoLock, Preserve) {
PM2I, 0x00000008,
PM2D, 0x00000008,
}
/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
OperationRegion(PIOR, SystemIO, 0x00000Cd6, 0x00000002)
Field(PIOR, ByteAcc, NoLock, Preserve) {
PIOI, 0x00000008,
PIOD, 0x00000008,
@ -88,7 +88,7 @@
IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
Offset(0x60), /* AcpiPm1EvgBlk */
P1EB, 16,
Offset(0xEE),
Offset(0xee),
UPWS, 3,
}
OperationRegion (P1E0, SystemIO, P1EB, 0x04)

16
src/soc/amd/stoneyridge/acpi/usb.asl
View File

@ -17,49 +17,49 @@
/* 0:12.0 - OHCI */
Device(UOH1) {
Name(_ADR, 0x00120000)
Name(_PRW, Package() {0x0B, 3})
Name(_PRW, Package() {0x0b, 3})
} /* end UOH1 */
/* 0:12.2 - EHCI */
Device(UOH2) {
Name(_ADR, 0x00120002)
Name(_PRW, Package() {0x0B, 3})
Name(_PRW, Package() {0x0b, 3})
} /* end UOH2 */
/* 0:13.0 - OHCI */
Device(UOH3) {
Name(_ADR, 0x00130000)
Name(_PRW, Package() {0x0B, 3})
Name(_PRW, Package() {0x0b, 3})
} /* end UOH3 */
/* 0:13.2 - EHCI */
Device(UOH4) {
Name(_ADR, 0x00130002)
Name(_PRW, Package() {0x0B, 3})
Name(_PRW, Package() {0x0b, 3})
} /* end UOH4 */
/* 0:16.0 - OHCI */
Device(UOH5) {
Name(_ADR, 0x00160000)
Name(_PRW, Package() {0x0B, 3})
Name(_PRW, Package() {0x0b, 3})
} /* end UOH5 */
/* 0:16.2 - EHCI */
Device(UOH6) {
Name(_ADR, 0x00160002)
Name(_PRW, Package() {0x0B, 3})
Name(_PRW, Package() {0x0b, 3})
} /* end UOH5 */
/* 0:10.0 - XHCI 0*/
Device(XHC0) {
Name(_ADR, 0x00100000)
Name(_PRW, Package() {0x0B, 4})
Name(_PRW, Package() {0x0b, 4})
} /* end XHC0 */
#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN
/* 0:10.1 - XHCI 1*/
Device(XHC1) {
Name(_ADR, 0x00100001)
Name(_PRW, Package() {0x0B, 4})
Name(_PRW, Package() {0x0b, 4})
} /* end XHC1 */
#endif