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util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC 

Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.

BUG=b:161772961
TEST=none

Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Nick Vaccaro 2020-10-02 12:59:43 -07:00 committed by Patrick Georgi
parent 1f8af4f49b
commit 6745056a06
3 changed files with 45 additions and 0 deletions
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32
src/soc/intel/tigerlake/spd/ddr4-spd-9.hex Normal file
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@ -0,0 +1,32 @@
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1
src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt
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@ -13,3 +13,4 @@ K4AAG165WA-BCWE,ddr4-spd-7.hex
H5AN8G6NCJR-XNC,ddr4-spd-1.hex
K4AAG165WA-BCTD,ddr4-spd-8.hex
H5ANAG6NDMR-XNC,ddr4-spd-2.hex
H5ANAG6NCJR-XNC,ddr4-spd-9.hex

12
util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt
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@ -191,6 +191,18 @@
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. 1.4, May. 2020
"name": "H5ANAG6NCJR-XNC",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 16,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
}
]
}