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mb/fb/watson/watson_v2: configure PCI bifurcation 

Watson V2 server has different PCIe bifurcation configuration, comparing to
Watson server.

Add a watson_v2 variant directory. Allow variant to customize UPD parameters.

Configure UPD parameters to define PCIe bifurcation configuration for Watson
V2 server.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3b57c64dea6f3a468336fcdb1e948dfcd897e60c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This commit is contained in:
Jonathan Zhang 2020-05-15 13:37:22 -07:00 committed by Philipp Deppenwiese
parent 631eac99ed
commit 674a825cd7
6 changed files with 89 additions and 0 deletions
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4
src/mainboard/facebook/watson/Kconfig
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@ -41,6 +41,10 @@ config CBFS_SIZE
hex hex
default 0x00800000 default 0x00800000
config VARIANT_DIR
string
default "watson_v2" if BOARD_FACEBOOK_WATSON_V2
config VBOOT_FWID_MODEL config VBOOT_FWID_MODEL
string string
default "$(CONFIG_MAINBOARD_VENDOR)_$(CONFIG_MAINBOARD_PART_NUMBER)" default "$(CONFIG_MAINBOARD_VENDOR)_$(CONFIG_MAINBOARD_PART_NUMBER)"

2
src/mainboard/facebook/watson/Makefile.inc
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@ -14,3 +14,5 @@
## ##
ramstage-y += irqroute.c ramstage-y += irqroute.c
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include

25
src/mainboard/facebook/watson/include/variants.h Normal file
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@ -0,0 +1,25 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 Google Inc.
* Copyright (C) Facebook, Inc. and its affiliates
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef BASEBOARD_VARIANTS_H
#define BASEBOARD_VARIANTS_H
#include <soc/romstage.h>
void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData);
#endif /* BASEBOARD_VARIANTS_H */

9
src/mainboard/facebook/watson/romstage.c
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@ -17,6 +17,7 @@
#include <stddef.h> #include <stddef.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <drivers/intel/fsp1_0/fsp_util.h> #include <drivers/intel/fsp1_0/fsp_util.h>
#include <variants.h>
/** /**
* /brief mainboard call for setup that needs to be done before fsp init * /brief mainboard call for setup that needs to be done before fsp init
@ -40,6 +41,14 @@ void late_mainboard_romstage_entry(void)
* /brief customize fsp parameters here if needed * /brief customize fsp parameters here if needed
*/ */
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
{
UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
/* Variant-specific memory params */
variant_romstage_fsp_init_params(UpdData);
}
__weak void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData)
{ {
} }

1
src/mainboard/facebook/watson/variants/watson_v2/Makefile.inc Normal file
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@ -0,0 +1 @@
romstage-y += romstage.c

48
src/mainboard/facebook/watson/variants/watson_v2/romstage.c Normal file
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@ -0,0 +1,48 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 Google Inc.
* Copyright (C) Facebook, Inc. and its affiliates
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/romstage.h>
#include <variants.h>
void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData)
{
/* Configure IOU1 as 4*4 lanes */
UpdData->ConfigIOU1_PciPort3 = 0;
/* Configure IOU2 as 2*4 lanes */
UpdData->ConfigIOU2_PciPort1 = 0;
/* Configure PCH PCIe ports as 8*1 lanes */
UpdData->PchPciPort1 = 1;
UpdData->PchPciPort2 = 1;
UpdData->PchPciPort3 = 1;
UpdData->PchPciPort4 = 1;
UpdData->PchPciPort5 = 1;
UpdData->PchPciPort6 = 1;
UpdData->PchPciPort7 = 1;
UpdData->PchPciPort8 = 1;
/* Enable hotplug for PCH PCIe ports */
UpdData->HotPlug_PchPciPort1 = 1;
UpdData->HotPlug_PchPciPort2 = 1;
UpdData->HotPlug_PchPciPort3 = 1;
UpdData->HotPlug_PchPciPort4 = 1;
UpdData->HotPlug_PchPciPort5 = 1;
UpdData->HotPlug_PchPciPort6 = 1;
UpdData->HotPlug_PchPciPort7 = 1;
UpdData->HotPlug_PchPciPort8 = 1;
}