mb/fb/watson/watson_v2: configure PCI bifurcation
Watson V2 server has different PCIe bifurcation configuration, comparing to Watson server. Add a watson_v2 variant directory. Allow variant to customize UPD parameters. Configure UPD parameters to define PCIe bifurcation configuration for Watson V2 server. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I3b57c64dea6f3a468336fcdb1e948dfcd897e60c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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@ -41,6 +41,10 @@ config CBFS_SIZE
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hex
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default 0x00800000
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config VARIANT_DIR
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string
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default "watson_v2" if BOARD_FACEBOOK_WATSON_V2
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config VBOOT_FWID_MODEL
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string
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default "$(CONFIG_MAINBOARD_VENDOR)_$(CONFIG_MAINBOARD_PART_NUMBER)"
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@ -14,3 +14,5 @@
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##
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ramstage-y += irqroute.c
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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@ -0,0 +1,25 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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* Copyright (C) Facebook, Inc. and its affiliates
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef BASEBOARD_VARIANTS_H
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#define BASEBOARD_VARIANTS_H
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#include <soc/romstage.h>
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void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData);
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#endif /* BASEBOARD_VARIANTS_H */
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@ -17,6 +17,7 @@
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#include <stddef.h>
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#include <soc/romstage.h>
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include <variants.h>
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/**
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* /brief mainboard call for setup that needs to be done before fsp init
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@ -40,6 +41,14 @@ void late_mainboard_romstage_entry(void)
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* /brief customize fsp parameters here if needed
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*/
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void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
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{
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UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
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/* Variant-specific memory params */
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variant_romstage_fsp_init_params(UpdData);
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}
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__weak void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData)
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{
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}
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@ -0,0 +1 @@
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romstage-y += romstage.c
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@ -0,0 +1,48 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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* Copyright (C) Facebook, Inc. and its affiliates
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/romstage.h>
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#include <variants.h>
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void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData)
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{
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/* Configure IOU1 as 4*4 lanes */
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UpdData->ConfigIOU1_PciPort3 = 0;
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/* Configure IOU2 as 2*4 lanes */
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UpdData->ConfigIOU2_PciPort1 = 0;
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/* Configure PCH PCIe ports as 8*1 lanes */
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UpdData->PchPciPort1 = 1;
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UpdData->PchPciPort2 = 1;
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UpdData->PchPciPort3 = 1;
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UpdData->PchPciPort4 = 1;
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UpdData->PchPciPort5 = 1;
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UpdData->PchPciPort6 = 1;
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UpdData->PchPciPort7 = 1;
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UpdData->PchPciPort8 = 1;
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/* Enable hotplug for PCH PCIe ports */
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UpdData->HotPlug_PchPciPort1 = 1;
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UpdData->HotPlug_PchPciPort2 = 1;
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UpdData->HotPlug_PchPciPort3 = 1;
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UpdData->HotPlug_PchPciPort4 = 1;
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UpdData->HotPlug_PchPciPort5 = 1;
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UpdData->HotPlug_PchPciPort6 = 1;
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UpdData->HotPlug_PchPciPort7 = 1;
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UpdData->HotPlug_PchPciPort8 = 1;
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}
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