soc/intel/icelake: Move power_state functions to pmutil.c
This patch ports CB:31787 and CB:31908 changes from CNL to ICL. This change moves soc_fill_power_state and soc_prev_sleep_state to pmutil.c. It allows the functions to be used across romstage and smm. Also fix GEN_PMCON bit checks as below: ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A and so this change updates the check for these bits to use GEN_PMCON_A instead of GEN_PMCON_B. Change-Id: Ib7ab95b7bbcc97a076d27a11db2105f7b976b521 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32506 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -210,3 +210,67 @@ int vbnv_cmos_failed(void)
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{
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return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
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}
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static inline int deep_s3_enabled(void)
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{
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uint32_t deep_s3_pol;
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deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
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return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
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}
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/* Return 0, 3, or 5 to indicate the previous sleep state. */
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int soc_prev_sleep_state(const struct chipset_power_state *ps,
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int prev_sleep_state)
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{
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/*
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* Check for any power failure to determine if this a wake from
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* S5 because the PCH does not set the WAK_STS bit when waking
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* from a true G3 state.
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*/
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if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
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prev_sleep_state = ACPI_S5;
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/*
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* If waking from S3 determine if deep S3 is enabled. If not,
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* need to check both deep sleep well and normal suspend well.
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* Otherwise just check deep sleep well.
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*/
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if (prev_sleep_state == ACPI_S3) {
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/* PWR_FLR represents deep sleep power well loss. */
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uint32_t mask = PWR_FLR;
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/* If deep s3 isn't enabled check the suspend well too. */
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if (!deep_s3_enabled())
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mask |= SUS_PWR_FLR;
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if (ps->gen_pmcon_a & mask)
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prev_sleep_state = ACPI_S5;
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}
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return prev_sleep_state;
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}
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void soc_fill_power_state(struct chipset_power_state *ps)
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{
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uint8_t *pmc;
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ps->tco1_sts = tco_read_reg(TCO1_STS);
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ps->tco2_sts = tco_read_reg(TCO2_STS);
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printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
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ps->tco1_sts, ps->tco2_sts);
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pmc = pmc_mmio_regs();
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ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
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ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
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ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
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ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
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printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
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ps->gen_pmcon_a, ps->gen_pmcon_b);
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printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
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ps->gblrst_cause[0], ps->gblrst_cause[1]);
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}
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@ -14,6 +14,5 @@
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#
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romstage-y += fsp_params.c
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romstage-y += power_state.c
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romstage-y += romstage.c
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romstage-y += systemagent.c
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@ -1,86 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/mmio.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/tco.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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static inline int deep_s3_enabled(void)
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{
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uint32_t deep_s3_pol;
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deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
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return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
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}
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/* Return 0, 3, or 5 to indicate the previous sleep state. */
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int soc_prev_sleep_state(const struct chipset_power_state *ps,
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int prev_sleep_state)
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{
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/*
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* Check for any power failure to determine if this a wake from
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* S5 because the PCH does not set the WAK_STS bit when waking
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* from a true G3 state.
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*/
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if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
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prev_sleep_state = ACPI_S5;
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/*
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* If waking from S3 determine if deep S3 is enabled. If not,
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* need to check both deep sleep well and normal suspend well.
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* Otherwise just check deep sleep well.
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*/
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if (prev_sleep_state == ACPI_S3) {
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/* PWR_FLR represents deep sleep power well loss. */
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uint32_t mask = PWR_FLR;
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/* If deep s3 isn't enabled check the suspend well too. */
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if (!deep_s3_enabled())
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mask |= SUS_PWR_FLR;
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if (ps->gen_pmcon_b & mask)
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prev_sleep_state = ACPI_S5;
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}
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return prev_sleep_state;
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}
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void soc_fill_power_state(struct chipset_power_state *ps)
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{
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uint8_t *pmc;
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ps->tco1_sts = tco_read_reg(TCO1_STS);
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ps->tco2_sts = tco_read_reg(TCO2_STS);
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printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
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ps->tco1_sts, ps->tco2_sts);
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pmc = pmc_mmio_regs();
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ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
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ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
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ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
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ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
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printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
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ps->gen_pmcon_a, ps->gen_pmcon_b);
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printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
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ps->gblrst_cause[0], ps->gblrst_cause[1]);
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}
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