arch/x86: introduce HAVE_CONFIGURABLE_APMC_SMI_PORT

Introduce the HAVE_CONFIGURABLE_APMC_SMI_PORT Kconfig option that when
not selected will result in a default implementation of
pm_acpi_smi_cmd_port to be included in the build that returns APM_CNT.
SoCs that provide their own pm_acpi_smi_cmd_port implementation, need to
select this Kconfig option.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaceb61b0f2a630d7afe2e0780b6a2a9806ea62f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit is contained in:
Felix Held 2023-12-14 20:49:59 +01:00
parent 3526b9fcaf
commit 6759ad39ad
5 changed files with 14 additions and 2 deletions

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@ -316,6 +316,13 @@ config HAVE_CF9_RESET_PREPARE
bool bool
depends on HAVE_CF9_RESET depends on HAVE_CF9_RESET
config HAVE_CONFIGURABLE_APMC_SMI_PORT
bool
help
SoCs that have a configurable APMC SMI command port, should select
this option and implement pm_acpi_smi_cmd_port() that returns the IO
port.
config PIRQ_ROUTE config PIRQ_ROUTE
bool bool
default n default n

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@ -336,3 +336,8 @@ smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
smm-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) += null_breakpoint.c smm-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) += null_breakpoint.c
smm-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c) smm-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c)
ifneq ($(CONFIG_HAVE_CONFIGURABLE_APMC_SMI_PORT),y)
ramstage-y += apmc_smi_port.c
smm-y += apmc_smi_port.c
endif

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@ -2,7 +2,7 @@
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */ /* default implementation of the !HAVE_CONFIGURABLE_APMC_SMI_PORT case */
uint16_t pm_acpi_smi_cmd_port(void) uint16_t pm_acpi_smi_cmd_port(void)
{ {
return APM_CNT; return APM_CNT;

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@ -20,5 +20,4 @@ all-y += ../qemu-i440fx/bootmode.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c
smm-y += smi.c
smm-y += memmap.c smm-y += memmap.c

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@ -1,5 +1,6 @@
config SOC_AMD_COMMON_BLOCK_SMI config SOC_AMD_COMMON_BLOCK_SMI
bool bool
select HAVE_CONFIGURABLE_APMC_SMI_PORT
help help
Select this option to add the common functions for setting up the SMI Select this option to add the common functions for setting up the SMI
configuration to the build. configuration to the build.