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In the RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set 

to zero, so for boards with RS780 not on CPU's HT chain 0, the function will
mis-configure the MMIO dst-link routing, and the following enable_pcie_bar3()
function will hang when it visits the MMIO.

The following patch fixes the problem, and is tested on a K8 board with RS780
on HT chain 1.

Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Liu Tao 2010-10-17 21:59:43 +00:00 committed by Uwe Hermann
parent dfecd2740b
commit 676d0298a1
2 changed files with 22 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/southbridge/amd/rs690/rs690_cmn.c
View File

@ -202,15 +202,23 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
{ {
/* K8 Function1 is address map */ /* K8 Function1 is address map */
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
if (in_out) { if (in_out) {
u32 dword, sblk;
/* Get SBLink value (HyperTransport I/O Hub Link ID). */
dword = pci_read_config32(k8_f0, 0x64);
sblk = (dword >> 8) & 0x3;
/* Fill MMIO limit/base pair. */
pci_write_config32(k8_f1, 0xbc, pci_write_config32(k8_f1, 0xbc,
(((pcie_base_add + 0x10000000 - (((pcie_base_add + 0x10000000 -
1) >> 8) & 0xffffff00) | 0x80); 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
pci_write_config32(k8_f1, 0xb4, pci_write_config32(k8_f1, 0xb4,
((mmio_base_add + 0x10000000 - (((mmio_base_add + 0x10000000 -
1) >> 8) & 0xffffff00); 1) >> 8) & 0xffffff00) | (sblk << 4));
pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
} else { } else {
pci_write_config32(k8_f1, 0xb8, 0); pci_write_config32(k8_f1, 0xb8, 0);

14
src/southbridge/amd/rs780/rs780_cmn.c
View File

@ -200,15 +200,23 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
{ {
/* K8 Function1 is address map */ /* K8 Function1 is address map */
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
if (in_out) { if (in_out) {
u32 dword, sblk;
/* Get SBLink value (HyperTransport I/O Hub Link ID). */
dword = pci_read_config32(k8_f0, 0x64);
sblk = (dword >> 8) & 0x3;
/* Fill MMIO limit/base pair. */
pci_write_config32(k8_f1, 0xbc, pci_write_config32(k8_f1, 0xbc,
(((pcie_base_add + 0x10000000 - (((pcie_base_add + 0x10000000 -
1) >> 8) & 0xffffff00) | 0x80); 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
pci_write_config32(k8_f1, 0xb4, pci_write_config32(k8_f1, 0xb4,
((mmio_base_add + 0x10000000 - (((mmio_base_add + 0x10000000 -
1) >> 8) & 0xffffff00); 1) >> 8) & 0xffffff00) | (sblk << 4));
pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
} else { } else {
pci_write_config32(k8_f1, 0xb8, 0); pci_write_config32(k8_f1, 0xb8, 0);