KBL: Update FSP headers - upgrade to FSP 2.5.0
Additional UPDs included with FSP 2.5.0:
FspsUpd.h:
*SataRstOptaneMemory
*Additional Upds for Core Ratio limit
FspmUpd.h:
*RingDownBin
*PcdDebugInterfaceFlags
*PcdSerialDebugBaudRate
*PcdSerialDebugLevel
*GtPllVoltageOffset
*RingPllVoltageOffset
*SaPllVoltageOffset
*McPllVoltageOffset
*RealtimeMemoryTiming
*EvLoader
*Avx3RatioOffset
CQ-DEPEND=CL:*388108,CL:*388109
BUG=None
BRANCH=None
TEST=Build and test on Soraka
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Change-Id: Id31ddd4595e36c91ba7c888688114c4dbe4db86a
Reviewed-on: https://review.coreboot.org/20123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Balaji Manigandan B
Martin Roth
parent
935ff1b208
commit
6771645678
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@ -840,7 +840,14 @@ typedef struct {
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/** Offset 0x02E2 - Core PLL voltage offset
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Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
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**/
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UINT16 CorePllVoltageOffset;
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UINT8 CorePllVoltageOffset;
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/** Offset 0x02E3 - Ring Downbin
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Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
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lower than the core ratio.<b>0: Disable</b>; 1: Enable.
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$EN_DIS
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**/
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UINT8 RingDownBin;
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/** Offset 0x02E4 - BCLK Adaptive Voltage Enable
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When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
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@ -1154,11 +1161,11 @@ typedef struct {
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**/
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UINT32 PcieRpEnableMask;
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/** Offset 0x050C - SerialIo Uart Debug
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Enable SerialIo Uart debug.
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0:Disable, 1:Enable
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/** Offset 0x050C - Debug Interfaces
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Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
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BIT2 - Not used.
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**/
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UINT8 PcdSerialDebugEnable;
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UINT8 PcdDebugInterfaceFlags;
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/** Offset 0x050D - SerialIo Uart Number Selection
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Select SerialIo Uart Controller for debug.
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@ -1190,9 +1197,67 @@ typedef struct {
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**/
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UINT8 PeciSxReset;
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/** Offset 0x0512
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/** Offset 0x0512 - PcdSerialDebugBaudRate
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Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
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3:9600, 4:19200, 6:56700, 7:115200
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**/
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UINT8 ReservedFspmUpd[14];
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UINT8 PcdSerialDebugBaudRate;
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/** Offset 0x0513 - PcdSerialDebugLevel
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Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
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Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
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Info & Verbose
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0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
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Error Warnings and Info, 5:Load Error Warnings Info and Verbose
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**/
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UINT8 PcdSerialDebugLevel;
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/** Offset 0x0514 - Enable or Disable EV Loader
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Enable or Disable EV Loader; <b>0: Disable;</b> 1: Enable.
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$EN_DIS
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**/
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UINT8 EvLoader;
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/** Offset 0x0515 - GT PLL voltage offset
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Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
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0x0:0xFF
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**/
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UINT8 GtPllVoltageOffset;
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/** Offset 0x0516 - Ring PLL voltage offset
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Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
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0x0:0xFF
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**/
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UINT8 RingPllVoltageOffset;
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/** Offset 0x0517 - System Agent PLL voltage offset
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Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
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0x0:0xFF
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**/
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UINT8 SaPllVoltageOffset;
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/** Offset 0x0518 - Memory Controller PLL voltage offset
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Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
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0x0:0xFF
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**/
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UINT8 McPllVoltageOffset;
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/** Offset 0x0519 - Realtime Memory Timing
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0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
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realtime memory timing changes after MRC_DONE.
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0: Disabled, 1: Enabled
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**/
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UINT8 RealtimeMemoryTiming;
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/** Offset 0x051A - AVX3 Ratio Offset
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0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
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vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
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**/
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UINT8 Avx3RatioOffset;
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/** Offset 0x051B
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**/
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UINT8 ReservedFspmUpd[5];
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} FSP_M_CONFIG;
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/** Fsp M Test Configuration
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@ -221,7 +221,7 @@ typedef struct {
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**/
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UINT8 XdciEnable;
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/** Offset 0x006D - Enable XHCI SSIC Eanble
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/** Offset 0x006D - Enable XHCI SSIC Enable
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Enable/disable XHCI SSIC port.
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$EN_DIS
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**/
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@ -1520,8 +1520,9 @@ typedef struct {
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**/
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UINT8 UnusedUpdSpace18;
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/** Offset 0x065C - PCH Pm WOL_OVR_WK_STS
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Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
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/** Offset 0x065C - PCH Port 61h Config Enable/Disable
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Used for the emulation feature for Port61h read. The port is trapped and the SMI
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handler will toggle bit4 according to the handler's internal state.
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$EN_DIS
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**/
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UINT8 PchPort61hEnable;
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@ -1959,9 +1960,15 @@ typedef struct {
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**/
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UINT8 Early8254ClockGatingEnable;
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/** Offset 0x0720
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/** Offset 0x0720 - PCH Sata Rst Optane Memory
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Optane Memory
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$EN_DIS
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**/
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UINT8 UnusedUpdSpace19[4];
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UINT8 SataRstOptaneMemory;
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/** Offset 0x0721
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**/
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UINT8 UnusedUpdSpace19[3];
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/** Offset 0x0724 - Pch PCIE device override table pointer
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The PCIe device table is being used to override PCIe device ASPM settings. This
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@ -2065,7 +2072,7 @@ typedef struct {
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**/
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UINT8 ChapDeviceEnable;
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/** Offset 0x0785 - Skip PAM regsiter lock
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/** Offset 0x0785 - Skip PAM register lock
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Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
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PAM registers will be locked by RC
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$EN_DIS
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@ -2145,7 +2152,8 @@ typedef struct {
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/** Offset 0x079C - 1-Core Ratio Limit
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1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
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1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal
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to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83
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to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit,
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6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 83
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**/
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UINT8 OneCoreRatioLimit;
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@ -2740,11 +2748,39 @@ typedef struct {
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**/
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UINT32 CpuS3ResumeData;
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/** Offset 0x0884 - ReservedCpuPostMemTest
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/** Offset 0x0884 - 5-Core Ratio Limit
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5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
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5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal
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to 1-Core Ratio Limit.Range is 0 to 83
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**/
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UINT8 FiveCoreRatioLimit;
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/** Offset 0x0885 - 6-Core Ratio Limit
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6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
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6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal
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to 1-Core Ratio Limit.Range is 0 to 83
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**/
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UINT8 SixCoreRatioLimit;
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/** Offset 0x0886 - 7-Core Ratio Limit
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7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
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7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal
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to 1-Core Ratio Limit.Range is 0 to 83
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**/
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UINT8 SevenCoreRatioLimit;
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/** Offset 0x0887 - 8-Core Ratio Limit
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8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
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8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal
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to 1-Core Ratio Limit.Range is 0 to 83
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**/
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UINT8 EightCoreRatioLimit;
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/** Offset 0x0888 - ReservedCpuPostMemTest
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Reserved for CPU Post-Mem Test
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$EN_DIS
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**/
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UINT8 ReservedCpuPostMemTest[6];
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UINT8 ReservedCpuPostMemTest[2];
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/** Offset 0x088A - SgxSinitDataFromTpm
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SgxSinitDataFromTpm default values
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