mb/system76/addw1: Add Adder WS 2 as a variant
Change-Id: I3965a90151bd9250a87dabc715d68a39699ff9e1 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Tim Crawford
Felix Held
parent
6a93a45242
commit
67772d27a6
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@ -181,6 +181,7 @@ The boards in this section are not real mainboards, but emulators.
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## System76
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- [Adder Workstation 1](system76/addw1.md)
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- [Adder Workstation 2](system76/addw2.md)
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- [Darter Pro 6](system76/darp6.md)
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- [Darter Pro 7](system76/darp7.md)
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- [Galago Pro 4](system76/galp4.md)
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@ -0,0 +1,66 @@
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# System76 Adder Workstation 2 (addw2)
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## Specs
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- CPU
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- Intel Core i7-10875H
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- Chipset
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- Intel HM470
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- EC
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- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
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- Graphics
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- NVIDIA GeForce RTX 2070 Super
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- eDP 15.6" 3840x2160@60Hz OLED (Samsung ATNA56WR06)
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- 1x HDMI
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- 1x Mini DisplayPort 1.4
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- 1x DisplayPort 1.4 over USB-C
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- Memory
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- Up to 64 (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
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- Networking
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- Gigabit Ethernet
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- M.2 PCIe/CNVi WiFi/Bluetooth
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- Intel Wi-Fi 6 AX200/AX201
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- Power
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- 230W (19.5V, 11.8A) AC barrel adapter
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- Chicony A17-230P1A, using a C5 power cord
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- 62Wh 6-cell Lithium-Ion battery
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- Sound
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- Internal speakers and microphone
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- Combined 3.5mm headhpone and microphone jack
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- Combined 3.5mm microphone and S/PDIF jack
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- HDMI, Mini DisplayPort, USB-C DisplayPort audio
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- Storage
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- M.2 PCIe NVMe Gen 3 or SATA 3 SSD
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- M.2 PCIe NVMe Gen 3 SSD
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- 2.5" SATA 3 SSD
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- SD card reader (RTS5250S)
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- USB
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- 1x USB Type-C with Thunderbolt 3
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- 1x USB 3.2 Gen 2 Type-C
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- 3x USB 3.2 Gen 1 Type-A
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- Dimensions
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- 35.890cm x 25.806cm x 2.997cm, 2.5kg
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## Flashing coreboot
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```eval_rst
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+---------------------+-----------------+
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| Type | Value |
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+=====================+=================+
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| Socketed flash | no |
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+---------------------+-----------------+
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| Vendor | Macronix |
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+---------------------+-----------------+
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| Model | MX25L12872F |
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+---------------------+-----------------+
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| Size | 16 MiB |
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+---------------------+-----------------+
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| Package | SOIC-8 |
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+---------------------+-----------------+
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| Internal flashing | yes |
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+---------------------+-----------------+
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| External flashing | yes |
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+---------------------+-----------------+
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```
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The flash chip (U60) is next to the battery connector.
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@ -1,4 +1,4 @@
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if BOARD_SYSTEM76_ADDW1
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if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
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select PCIEXP_HOTPLUG
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select SOC_INTEL_CANNONLAKE_PCH_H
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select SOC_INTEL_COFFEELAKE if BOARD_SYSTEM76_ADDW1
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select SOC_INTEL_COMETLAKE_1 if BOARD_SYSTEM76_ADDW2
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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@ -31,18 +32,21 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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default "addw1" if BOARD_SYSTEM76_ADDW1
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default "addw2" if BOARD_SYSTEM76_ADDW2
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config MAINBOARD_PART_NUMBER
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default "addw1" if BOARD_SYSTEM76_ADDW1
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default "addw2" if BOARD_SYSTEM76_ADDW2
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "Adder WS"
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config MAINBOARD_VERSION
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default "addw1" if BOARD_SYSTEM76_ADDW1
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default "addw2" if BOARD_SYSTEM76_ADDW2
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config CBFS_SIZE
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default 0xA00000
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@ -1,2 +1,5 @@
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config BOARD_SYSTEM76_ADDW1
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bool "addw1"
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config BOARD_SYSTEM76_ADDW2
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bool "addw2"
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@ -0,0 +1,2 @@
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Board name: addw2
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Release year: 2020
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Binary file not shown.
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@ -0,0 +1,263 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
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PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
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PAD_NC(GPD2, NONE),
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PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
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PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
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PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
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PAD_NC(GPD6, NONE),
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PAD_CFG_GPI(GPD7, NONE, DEEP), // RESERVED STRAP
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PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
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PAD_NC(GPD9, NONE),
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PAD_NC(GPD10, NONE),
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PAD_NC(GPD11, NONE),
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/* ------- GPIO Group GPP_A ------- */
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PAD_NC(GPP_A0, NONE),
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PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
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PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
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PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
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PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
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PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SCI#_GPP_A7
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // ECCLKRUN#
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBD
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PAD_NC(GPP_A10, DN_20K),
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PAD_NC(GPP_A11, UP_20K),
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PAD_NC(GPP_A12, NONE),
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PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
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PAD_CFG_GPI_APIC(GPP_A14, NONE, PLTRST, EDGE_SINGLE, INVERT), // TCHPD_INT#
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PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PW_ACK#
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PAD_NC(GPP_A16, DN_20K),
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PAD_CFG_GPI(GPP_A17, NONE, DEEP), // AMP_TYPE_DET
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PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON
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PAD_NC(GPP_A19, NONE),
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PAD_CFG_GPI(GPP_A20, NONE, DEEP), // PEX_WAKE#
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_PAD_CFG_STRUCT(GPP_A21, 0x46080100, 0x0000), // EAPD_MODE
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PAD_NC(GPP_A22, NONE),
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PAD_CFG_GPI(GPP_A23, NONE, DEEP), // DGPU_BOARD_ID
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/* ------- GPIO Group GPP_B ------- */
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_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ#
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PAD_NC(GPP_B1, NONE),
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PAD_NC(GPP_B2, NONE),
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PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN
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PAD_NC(GPP_B4, NONE),
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ#
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PAD_NC(GPP_B6, NONE),
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PAD_CFG_GPO(GPP_B7, 0, DEEP), // GPP_B7_CR_RST#
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PAD_CFG_GPI(GPP_B8, NONE, DEEP), // GPP_B8_CR_WAKE#
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PAD_NC(GPP_B9, NONE),
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // GLAN_CLKREQ#
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PAD_NC(GPP_B11, NONE),
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
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_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), // PLT_RST#
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
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PAD_NC(GPP_B15, NONE),
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PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B17, NONE),
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PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT STRAP
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PAD_NC(GPP_B19, NONE),
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_PAD_CFG_STRUCT(GPP_B20, 0x42840101, 0x0000), // SMI#_GPP_B20
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PAD_NC(GPP_B21, NONE),
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PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BIOS BOOT STRAP
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PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI-OOB STRAP
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
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PAD_CFG_GPI(GPP_C2, NONE, DEEP), // CNVI_WAKE#
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PAD_NC(GPP_C3, NONE),
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PAD_NC(GPP_C4, NONE),
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PAD_CFG_GPI(GPP_C5, NONE, DEEP), // WLAN_WAKEUP#
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PAD_NC(GPP_C6, NONE),
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PAD_NC(GPP_C7, NONE),
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PAD_NC(GPP_C8, NONE),
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PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID1
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PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID2
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PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
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PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
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PAD_CFG_GPI(GPP_C13, NONE, PLTRST), // TPM_DET
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PAD_CFG_GPO(GPP_C14, 1, DEEP), // GPU_EVENT#
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PAD_CFG_GPI(GPP_C15, NONE, DEEP),
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PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // TP_DAT_PCH_I2C0
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PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // TP_CLK_PCH_I2C0
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PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C1_SDA
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PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C1_SCL
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//PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
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//PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
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PAD_CFG_GPI(GPP_C22, NONE, DEEP), // UART2_RTS#
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PAD_CFG_GPI(GPP_C23, NONE, DEEP), // UART2_CTS#
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/* ------- GPIO Group GPP_D ------- */
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PAD_NC(GPP_D0, NONE),
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PAD_NC(GPP_D1, NONE),
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PAD_NC(GPP_D2, NONE),
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PAD_NC(GPP_D3, NONE),
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PAD_NC(GPP_D4, NONE),
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST#
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
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PAD_NC(GPP_D7, NONE),
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PAD_NC(GPP_D8, NONE),
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PAD_NC(GPP_D9, NONE),
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PAD_NC(GPP_D10, NONE),
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PAD_NC(GPP_D11, NONE),
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PAD_NC(GPP_D12, NONE),
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PAD_NC(GPP_D13, NONE),
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PAD_NC(GPP_D14, NONE),
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PAD_NC(GPP_D15, NONE),
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PAD_NC(GPP_D16, NONE),
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PAD_NC(GPP_D17, NONE),
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PAD_NC(GPP_D18, NONE),
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PAD_NC(GPP_D19, NONE),
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PAD_NC(GPP_D20, NONE),
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PAD_NC(GPP_D21, NONE),
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PAD_NC(GPP_D22, NONE),
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PAD_NC(GPP_D23, NONE),
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/* ------- GPIO Group GPP_E ------- */
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PAD_NC(GPP_E0, NONE),
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PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
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PAD_NC(GPP_E2, NONE),
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PAD_NC(GPP_E3, NONE),
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PAD_NC(GPP_E4, NONE),
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PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SATA_DEVSLP1
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PAD_NC(GPP_E6, NONE),
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PAD_NC(GPP_E7, NONE),
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATAHDD_LED#
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PAD_NC(GPP_E9, NONE), // USB_OC0# (test point)
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PAD_NC(GPP_E10, NONE), // USB_OC1# (test point)
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PAD_NC(GPP_E11, NONE), // USB_OC2# (test point)
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PAD_NC(GPP_E12, NONE), // USB_OC3# (test point)
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/* ------- GPIO Group GPP_F ------- */
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PAD_NC(GPP_F0, NONE),
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PAD_NC(GPP_F1, NONE),
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PAD_NC(GPP_F2, NONE),
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PAD_CFG_GPO(GPP_F3, 0, DEEP), // GPP_F3_LAN_RST#
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PAD_CFG_GPI(GPP_F4, NONE, DEEP), // GPP_F4_TBT_RST#
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PAD_NC(GPP_F5, NONE),
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PAD_NC(GPP_F6, NONE),
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PAD_NC(GPP_F7, NONE),
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PAD_NC(GPP_F8, NONE),
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PAD_CFG_GPO(GPP_F9, 0, DEEP), // PS8331_SW
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PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS RECOVERY STRAP
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PAD_NC(GPP_F11, NONE),
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PAD_NC(GPP_F12, NONE),
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PAD_NC(GPP_F13, NONE),
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PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_H
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PAD_NC(GPP_F15, NONE), // USB_OC4# (test point)
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PAD_NC(GPP_F16, NONE), // USB_OC5# (test point)
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PAD_NC(GPP_F17, NONE), // USB_OC6# (test point)
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PAD_NC(GPP_F18, NONE), // USB_OC7# (test point)
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
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//PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
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//PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
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/* ------- GPIO Group GPP_G ------- */
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PAD_CFG_GPI(GPP_G0, NONE, DEEP), // GSYNC_DET
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PAD_NC(GPP_G1, NONE),
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PAD_CFG_GPI(GPP_G2, NONE, DEEP), // DDS_DET
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PAD_NC(GPP_G3, NONE),
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PAD_NC(GPP_G4, NONE),
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PAD_NC(GPP_G5, NONE),
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PAD_CFG_GPI(GPP_G6, NONE, DEEP), // SWI#_GPP_G6
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PAD_NC(GPP_G7, NONE),
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/* ------- GPIO Group GPP_H ------- */
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PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
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PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CR_CLKREQ#
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PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
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PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ#
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ#
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PAD_NC(GPP_H5, NONE),
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PAD_CFG_GPO(GPP_H6, 1, DEEP), // PCIE_SSD1_RST#
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PAD_CFG_GPO(GPP_H7, 1, DEEP), // PCIE_SSD2_RST#
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PAD_CFG_GPI(GPP_H8, NONE, DEEP), // GPP_H8_LAN_RST#
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_PAD_CFG_STRUCT(GPP_H9, 0x40880100, 0x0000), // GPP_H9_TBT_WAKE#
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PAD_NC(GPP_H10, NONE),
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PAD_NC(GPP_H11, NONE),
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PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING MODE STRAP
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PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
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PAD_NC(GPP_H14, NONE),
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PAD_CFG_GPI(GPP_H15, NONE, DEEP), // RESERVED STRAP
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PAD_CFG_GPO(GPP_H16, 1, DEEP), // TBT_RTD3_PWR_EN_R
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PAD_CFG_GPO(GPP_H17, 1, PLTRST), // TBT_FORCE_PWR_R
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PAD_NC(GPP_H18, NONE),
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PAD_CFG_GPO(GPP_H19, 0, DEEP), // GPP_H19_CR_AUX33
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PAD_CFG_GPO(GPP_H20, 0, DEEP), // GPP_H20_CR_MV33
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PAD_CFG_GPI(GPP_H21, NONE, DEEP),
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PAD_NC(GPP_H22, NONE),
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_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT#
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/* ------- GPIO Group GPP_I ------- */
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_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000), // MDP_B_HPD
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_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000), // HDMI_HPD
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_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000), // MDP_E_HPD
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000), // PS8330B_HPD
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD
|
||||
PAD_CFG_TERM_GPO(GPP_I5, 1, UP_20K, PLTRST), // TBT_GPIO_RST#
|
||||
PAD_NC(GPP_I6, NONE),
|
||||
PAD_NC(GPP_I7, NONE),
|
||||
PAD_CFG_GPO(GPP_I8, 1, DEEP), // SSD1_PWR_EN
|
||||
PAD_CFG_GPO(GPP_I9, 1, DEEP), // SSD2_PWR_EN
|
||||
PAD_NC(GPP_I10, NONE),
|
||||
PAD_NC(GPP_I11, NONE),
|
||||
PAD_CFG_GPO(GPP_I12, 1, DEEP), // SATA_PWR_EN
|
||||
PAD_NC(GPP_I13, NONE),
|
||||
PAD_NC(GPP_I14, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
|
||||
PAD_CFG_GPO(GPP_J1, 1, DEEP), // GPP_J1
|
||||
PAD_NC(GPP_J2, NONE),
|
||||
PAD_NC(GPP_J3, NONE),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
|
||||
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
|
||||
PAD_NC(GPP_J10, NONE),
|
||||
PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_K ------- */
|
||||
PAD_CFG_GPO(GPP_K0, 0, DEEP), // GPP_K0_SPK_MUTE
|
||||
PAD_CFG_GPO(GPP_K1, 0, DEEP), // GPP_K1_WOOFER_MUTE
|
||||
PAD_NC(GPP_K2, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), // SCI#_GPP_K3
|
||||
PAD_NC(GPP_K4, NONE),
|
||||
PAD_NC(GPP_K5, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_GPP_K6
|
||||
PAD_CFG_GPI(GPP_K7, NONE, DEEP), // GPP_K7_LAN_WAKEUP#
|
||||
PAD_CFG_GPO(GPP_K8, 0, DEEP), // GPP_K8_LAN_RTD3
|
||||
PAD_NC(GPP_K9, NONE),
|
||||
PAD_NC(GPP_K10, NONE),
|
||||
PAD_NC(GPP_K11, NONE),
|
||||
PAD_CFG_GPO(GPP_K12, 0, DEEP), // GPP_K12_PLVDD_SEL
|
||||
PAD_NC(GPP_K13, NONE),
|
||||
PAD_CFG_GPO(GPP_K14, 0, DEEP), // GPP_K14_TEST_R
|
||||
_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000), // GPP_K15_INTP_OUT
|
||||
PAD_NC(GPP_K16, NONE),
|
||||
PAD_NC(GPP_K17, NONE),
|
||||
PAD_CFG_GPO(GPP_K18, 1, DEEP), // GPP_K18_TBT_WAKE#
|
||||
PAD_CFG_GPI(GPP_K19, NONE, DEEP), // SMI#_GPP_K19
|
||||
PAD_NC(GPP_K20, NONE),
|
||||
PAD_NC(GPP_K21, NONE),
|
||||
PAD_CFG_GPO(GPP_K22, 0, DEEP), // DGPU_OVRM
|
||||
PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWR_OK
|
||||
};
|
||||
|
||||
void variant_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
|
||||
};
|
||||
|
||||
void variant_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155865e1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865e1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D)
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A)
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // CENTER/LFE (Port-G)
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // SIDE (Port-H)
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040), // MIC1 (Port-B)
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // MIC2 (Port-F)
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // LINE1 (Port-C)
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110), // LINE2 (Port-E)
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), // PCBEEP
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150), // S/PDIF-OUT
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
// Enable DMIC microphone on ALC1220
|
||||
0x02050036,
|
||||
0x02042a6a,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
chip soc/intel/cannonlake
|
||||
# Serial I/O
|
||||
register "SerialIoDevMode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
|
||||
[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x65e1 inherit
|
||||
|
||||
device pci 15.0 on # I2C #0
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PNP0C50""
|
||||
register "generic.desc" = ""Synaptics Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A14_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 2c on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue