util/autoport: correct build errors of produced files
Change-Id: I8d1a6af6f1d70268f17692bee130c08502082c97 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons
Nico Huber
parent
38a4f2a974
commit
6779d2352c
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@ -20,13 +20,12 @@ const u32 cim_verb_data[] = {
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`)
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for _, codec := range ctx.InfoSource.GetAzaliaCodecs() {
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fmt.Fprintf(az, "\t0x%08x, /* Codec Vendor / Device ID: %s */\n",
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fmt.Fprintf(az, "\t0x%08x,\t/* Codec Vendor / Device ID: %s */\n",
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codec.VendorID, codec.Name)
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fmt.Fprintf(az, "\t0x%08x, /* Subsystem ID */\n",
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fmt.Fprintf(az, "\t0x%08x,\t/* Subsystem ID */\n",
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codec.SubsystemID)
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fmt.Fprintf(az, "\n\t0x%08x, /* Number of 4 dword sets */\n",
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fmt.Fprintf(az, "\t%d,\t\t/* Number of 4 dword sets */\n",
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len(codec.PinConfig)+1)
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fmt.Fprintf(az, "\t/* NID 0x01: Subsystem ID. */\n")
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fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n",
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codec.CodecNo, codec.SubsystemID)
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@ -38,10 +37,10 @@ const u32 cim_verb_data[] = {
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sort.Ints(keys)
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for _, nid := range keys {
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fmt.Fprintf(az, "\n\t/* NID 0x%02x. */\n", nid)
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fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n",
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codec.CodecNo, nid, codec.PinConfig[nid])
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}
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az.WriteString("\n");
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}
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az.WriteString(
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@ -52,7 +51,7 @@ const u32 pc_beep_verbs[0] = {};
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AZALIA_ARRAY_SIZES;
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`)
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PutPCIDev(addr, "Audio controller")
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PutPCIDev(addr, "")
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}
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func init() {
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@ -41,6 +41,7 @@ func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) {
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gpio := Create(ctx, "gpio.c")
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defer gpio.Close()
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AddBootBlockFile("gpio.c", "")
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AddROMStageFile("gpio.c", "")
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Add_gpl(gpio)
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@ -279,20 +280,22 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
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PutPCIDevParent(addr, "PCI-LPC bridge", "lpc")
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/platform.asl",
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File: "southbridge/intel/common/acpi/platform.asl",
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})
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl",
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Comment: "global NVS and variables",
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File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl",
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})
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl",
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File: "southbridge/intel/common/acpi/sleepstates.asl",
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})
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DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/pch.asl",
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})
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sb := Create(ctx, "romstage.c")
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AddBootBlockFile("early_init.c", "")
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AddROMStageFile("early_init.c", "")
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sb := Create(ctx, "early_init.c")
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defer sb.Close()
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Add_gpl(sb)
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sb.WriteString(`/* FIXME: Check if all includes are needed. */
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@ -305,25 +308,13 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
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#include <device/pci_ops.h>
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#include <device/pnp_ops.h>
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#include <console/console.h>
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#include <bootblock_common.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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void pch_enable_lpc(void)
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{
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`)
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RestorePCI16Simple(sb, addr, 0x82)
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RestorePCI16Simple(sb, addr, 0x80)
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sb.WriteString(`}
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void mainboard_rcba_config(void)
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{
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`)
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sb.WriteString("}\n\n")
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sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n")
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currentMap := map[uint32]int{
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@ -360,13 +351,14 @@ void mainboard_rcba_config(void)
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guessedMap := GuessSPDMap(ctx)
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sb.WriteString(`
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void mainboard_early_init(int s3resume)
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void bootblock_mainboard_early_init(void)
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{
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}
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`)
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RestorePCI16Simple(sb, addr, 0x82)
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void mainboard_config_superio(void)
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{
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}
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RestorePCI16Simple(sb, addr, 0x80)
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sb.WriteString(`}
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/* FIXME: Put proper SPD map here. */
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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@ -394,7 +386,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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// the lid is open by default.
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/* The lid is open by default. */
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gnvs->lids = 1;
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gnvs->tcrt = 100;
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@ -22,13 +22,13 @@ func FIXMEEC(ctx Context) {
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ap.WriteString(
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`Method(_WAK,1)
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{
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/* FIXME: EC support */
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/* FIXME: EC support */
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Return(Package(){0,0})
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}
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Method(_PTS,1)
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{
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/* FIXME: EC support */
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/* FIXME: EC support */
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}
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`)
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@ -77,6 +77,7 @@ type SouthBridger interface {
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}
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var SouthBridge SouthBridger
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var BootBlockFiles map[string]string = map[string]string{}
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var ROMStageFiles map[string]string = map[string]string{}
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var RAMStageFiles map[string]string = map[string]string{}
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var SMMFiles map[string]string = map[string]string{}
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@ -154,6 +155,10 @@ func sanitize(inp string) string {
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return result
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}
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func AddBootBlockFile(Name string, Condition string) {
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BootBlockFiles[Name] = Condition
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}
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func AddROMStageFile(Name string, Condition string) {
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ROMStageFiles[Name] = Condition
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}
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@ -190,8 +195,7 @@ func writeMF(mf *os.File, files map[string]string, category string) {
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if condition == "" {
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fmt.Fprintf(mf, "%s-y += %s\n", category, file)
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} else {
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fmt.Fprintf(mf, "%s-$(%s) += %s\n", category,
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condition, file)
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fmt.Fprintf(mf, "%s-$(%s) += %s\n", category, condition, file)
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}
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}
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}
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@ -757,9 +761,10 @@ func main() {
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AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT")
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}
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if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 {
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if len(BootBlockFiles) > 0 || len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 {
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mf := Create(ctx, "Makefile.inc")
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defer mf.Close()
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writeMF(mf, BootBlockFiles, "bootblock")
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writeMF(mf, ROMStageFiles, "romstage")
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writeMF(mf, RAMStageFiles, "ramstage")
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writeMF(mf, SMMFiles, "smm")
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@ -854,17 +859,18 @@ func main() {
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dsdt.WriteString(
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`
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#include <arch/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI 2.0 and up
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0x02, /* DSDT revision: ACPI 2.0 and up */
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20141018 // OEM revision
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0x20141018 /* OEM revision */
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)
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{
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/* Some generic macros */
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#include "acpi/platform.asl"
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`)
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@ -8,7 +8,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
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/* FIXME:XX Move this somewhere else. */
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MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
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MainboardEnable += (` /* FIXME: fix those values*/
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MainboardEnable += (` /* FIXME: fix these values. */
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install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
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GMA_INT15_PANEL_FIT_DEFAULT,
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GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
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@ -37,7 +37,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
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DevTree = DevTreeNode{
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Chip: "northbridge/intel/sandybridge",
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MissingParent: "northbridge",
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Comment: "FIXME: check gfx.ndid and gfx.did",
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Comment: "FIXME: GPU registers may not always apply.",
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Registers: map[string]string{
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"gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
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"gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
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@ -52,9 +52,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
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"gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
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"gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0),
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"gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000),
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/* FIXME:XX hardcoded. */
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"gfx.ndid": "3",
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"gfx.did": "{ 0x80000100, 0x80000240, 0x80000410 }",
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},
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Children: []DevTreeNode{
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{
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@ -95,8 +92,8 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
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ChildPCIBus: 0,
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PCISlots: []PCISlot{
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PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PEG"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "iGPU"},
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},
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},
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},
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@ -134,7 +131,7 @@ func init() {
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0x0112, 0x0116, 0x0122, 0x0126,
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0x0152, 0x0156, 0x0162, 0x0166,
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} {
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RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
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RegisterPCI(0x8086, id, GenericVGA{GenericPCI{}})
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}
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/* PCIe bridge */
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