GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK. 

Also:

Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device
on various PCI bus:device.function locations.
Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.

Thus, instead of hardcoding PCI bus:device.function numbers such as
PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which
works the same on all boards.

As an additional benefit this patch also gets rid of one .c file include
in romstage.c.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-10-07 16:24:28 +00:00
parent 6f2d20ec49
commit 6798b47802
23 changed files with 47 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/a-trend/atc-6220/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -53,9 +52,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/a-trend/atc-6240/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -53,9 +52,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/abit/be6-ii_v2_0/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -56,9 +55,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/asus/p2b-d/romstage.c
View File

@ -27,7 +27,6 @@
#include <stdlib.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -56,9 +55,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/asus/p2b-ds/romstage.c
View File

@ -27,7 +27,6 @@
#include <stdlib.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -56,9 +55,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/asus/p2b-f/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -56,9 +55,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/asus/p2b-ls/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -55,9 +54,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/asus/p2b/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -53,9 +52,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/asus/p3b-f/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "southbridge/intel/i82371eb/i82371eb_early_pm.c"
#include "northbridge/intel/i440bx/raminit.h"
@ -88,9 +87,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
enable_smbus();
enable_pm();

4
src/mainboard/azza/pt-6ibd/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -56,9 +55,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/biostar/m6tba/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -54,9 +53,6 @@ void main(unsigned long bist)
report_bist_failure(bist);
enable_smbus();
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();

4
src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -56,9 +55,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 14, 0)); /* ISA bridge is 00:14.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/gigabyte/ga-6bxc/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -54,9 +53,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/gigabyte/ga-6bxe/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -55,9 +54,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/msi/ms6119/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -53,9 +52,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/msi/ms6147/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -53,9 +52,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/msi/ms6156/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -53,9 +52,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/nokia/ip530/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -53,9 +52,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0) ); /* ISA bridge at 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -54,9 +53,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

4
src/mainboard/tyan/s1846/romstage.c
View File

@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@ -53,9 +52,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
dump_spd_registers();
sdram_set_registers();

6
src/southbridge/intel/i82371eb/Kconfig
View File

@ -1,4 +1,10 @@
config SOUTHBRIDGE_INTEL_I82371EB
bool
select IOAPIC
select TINY_BOOTBLOCK
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82371eb/bootblock.c"
depends on SOUTHBRIDGE_INTEL_I82371EB

26
src/southbridge/intel/i82371eb/bootblock.c Normal file
View File

@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
static void bootblock_southbridge_init(void)
{
i82371eb_enable_rom();
}

16
src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
View File

@ -19,11 +19,25 @@
*/
#include <stdint.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_ids.h>
#include "i82371eb.h"
static void i82371eb_enable_rom(device_t dev)
static void i82371eb_enable_rom(void)
{
u16 reg16;
device_t dev;
/*
* Note: The Intel 82371AB/EB/MB ISA device can be on different
* PCI bus:device.function locations on different boards.
* Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
* But scanning for the PCI IDs (instead of hardcoding
* bus/device/function numbers) works on all boards.
*/
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
/* Enable access to the whole ROM, disable ROM write access. */
reg16 = pci_read_config16(dev, XBCS);