mb/google/guybrush/var/nipperkin: Override GPIO configuration
SOC_PEN_DETECT_ODL, SOC_SAR_INT_L and WWAN_AUX_RESET_L are not connected in nipperkin. Override those GPIO configurations. BUG=None TEST=Build and boot to OS in Nipperkin. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7e497f83593472ecf4927e5379e1dd7786e77e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
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# SPDX-License-Identifier: GPL-2.0-or-later
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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subdirs-y += ./memory
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <baseboard/variants.h>
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static const struct soc_amd_gpio override_gpio_table[] = {
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/* Unused TP1056 */
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PAD_NC(GPIO_4),
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/* Unused TP1063 */
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PAD_NC(GPIO_17),
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PAD_NC(GPIO_18),
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};
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static const struct soc_amd_gpio override_early_gpio_table[] = {
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PAD_NC(GPIO_18),
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};
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static const struct soc_amd_gpio override_pcie_gpio_table[] = {
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PAD_NC(GPIO_18),
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};
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const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
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{
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*size = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
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{
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*size = ARRAY_SIZE(override_early_gpio_table);
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return override_early_gpio_table;
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}
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const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
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{
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*size = ARRAY_SIZE(override_pcie_gpio_table);
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return override_pcie_gpio_table;
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}
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